Corey Schuhen
242759a600
Use Result instead of Option for Frame creation.
2024-03-13 17:46:50 +10:00
Corey Schuhen
12a3af5043
Shared frame types.
...
Remove BXCAN speciffic id and frame modules
Remove SizedClassicData
2024-03-13 17:46:50 +10:00
Dario Nieuwenhuis
35f284ec22
Merge pull request #2691 from caleb-garrett/cryp-dma
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STM32 CRYP DMA
2024-03-12 19:30:20 +00:00
Dario Nieuwenhuis
9101b9eb01
Merge pull request #2650 from cschuhen/feature/bxcan_pac
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Use stm32-metapac for BXCAN.
2024-03-12 19:05:22 +00:00
Caleb Garrett
2634a57098
Correct cryp CI build issues.
2024-03-12 15:05:22 -04:00
Caleb Garrett
1ec9fc58f4
Add async CRYP to test.
2024-03-12 14:52:34 -04:00
Caleb Garrett
61050a16d5
Add CRYP DMA support. Updated example.
2024-03-12 12:01:14 -04:00
Timo Kröger
30cdc6c9c5
[UCPD] Disable dead-battery resistor for all families
...
Using the code from PR #2683 , thank you @ExplodingWaffle
Removes the dead-battery as selectable option because its unclear if
it can be re-enabled. Also there is no use case for it because the same
resistor can be configured with the sink option.
2024-03-12 08:49:27 +01:00
Timo Kröger
eeb033caf0
[UCPD] Disable RCC clock on drop
2024-03-12 08:14:42 +01:00
Timo Kröger
89504f5162
[UCPD] Split into CC and PD phy
...
PD3.0 spec requires concurrent control of CC resistors for collision avoidance.
Needed to introduce some "ref counting" (its just a bool) for drop code.
2024-03-12 08:14:42 +01:00
Timo Kröger
99854ff840
[UCPD] Fix build for devices with GPDMA
...
Do not use a flag that is DMA/BDMA only, not required anyway
the transfer should run in the background nevertheless
2024-03-12 08:14:42 +01:00
Timo Kröger
ff8129a6a6
[UCPD] Implement hard reset transmission
2024-03-12 08:14:42 +01:00
Timo Kröger
c1efcbba2d
[UCPD] Receive hard resets
2024-03-12 08:14:42 +01:00
Timo Kröger
b7972048a1
[UCPD] Improve example and defmt Format for enums
2024-03-12 08:14:42 +01:00
Timo Kröger
5e271ff31b
[UCPD] Combine RX and TX
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`select(rx.receive(), tx.transmit()` had subtle interrupt enable race conditions.
Combine receiver and transmitter into one new `PdPhy` struct to disallow the
problematic pattern.
Scanning through the USB PD 2.0 specification there is no need to have RX and TX
running concurrently (after all the USB PD communication is half-duplex).
2024-03-12 08:14:42 +01:00
Timo Kröger
36a9918921
[UCPD] Implement PD transmitter
2024-03-12 08:14:42 +01:00
Timo Kröger
984d5bbc72
[UCPD] Implement PD receiver
2024-03-12 08:14:42 +01:00
Timo Kröger
4d0e383816
[UCPD] Prepare for PD communication implementation
2024-03-12 08:14:42 +01:00
Timo Kröger
a3b1222617
[UCPD] Improve Type-C CC handling
...
* Improved interrupt handling: Clear flags in ISR, check state change in future
* Disable pull-up/pull-down resistors and voltage monitor on drop
* nightly rustfmt
2024-03-12 08:14:42 +01:00
Timo Kröger
d99fcfd0c2
[UCPD] Configuration Channel (CC) handling
2024-03-12 08:14:42 +01:00
Timo Kröger
aa1411e2c7
[UCPD] Prepare interrupt handle
2024-03-12 08:14:41 +01:00
Timo Kröger
8a255b375b
[UCPD] Instance and Pin Traits
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Skip FRSTX pin for now. Its available twice in the device JSON as
FRSTX1 and FRSTX2 both with the same pins as targets.
I don’t know enough about the FRS (fast role switch) feature to
understand if that is correct and how to handle the pins.
2024-03-12 08:14:41 +01:00
Dario Nieuwenhuis
1ef02e5384
Merge pull request #2683 from ExplodingWaffle/ucpd-dbdis
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stm32: add disable_ucpdx_dead_battery
2024-03-11 23:36:15 +00:00
Harry Brooke
d4869b83fc
disable -> enable. also extracted to function for easy refactoring later
2024-03-11 23:03:09 +00:00
Dominic
b6a383811a
Improve panic message when requesting frequency higher than clock
...
Previously it would panic with message "unreachable", which isn't
particularly clear about what the problem is and how to fix it.
2024-03-11 17:52:18 +01:00
Caleb Garrett
6e9e8eeb5f
Refactored cryp din/dout into functions.
2024-03-11 11:08:02 -04:00
Harry Brooke
096d147dce
stm32: add disable_ucpdx_dead_battery
2024-03-11 11:42:04 +00:00
Harry Brooke
f761f721bc
fix ci
2024-03-10 22:51:42 +00:00
Caleb Garrett
4a5b6e05fb
Correct more CI build issues.
2024-03-10 17:33:40 -04:00
Caleb Garrett
50a7ada0bb
Fixed DMA CI build issues.
2024-03-10 17:28:53 -04:00
Caleb Garrett
e92094986d
Add DMA request priority as transfer option.
2024-03-10 16:53:37 -04:00
Adam Greig
b456addb2b
stm32: bump metapac version
2024-03-09 20:13:20 +00:00
Harry Brooke
2d7ec281e8
stm32/rcc: wait for peripheral clock to be active. also, hold the peripheral reset while enabling the clock.
2024-03-09 18:24:31 +00:00
Dominic
71179fa818
Check for CPU_FREQ_BOOST
2024-03-09 11:55:09 +01:00
Dominic
fadffc5061
Fix incorrect D1CPRE max for STM32H7 RM0468
2024-03-09 11:55:09 +01:00
Ralf
b7bb4b23f8
STM32 SimplePwm: Fix regression and re-enable output pin
...
PR #2499 implemented timer hierarchy, but removed enable_outputs()
from trait CaptureCompare16bitInstance and from SimplePwm.
This functions is required for advanced timers to set bit BDTR.MOE
and to enable the output signal.
2024-03-08 11:18:45 +01:00
Karun
fda6e3fb8c
Resolve rustfmt issue and unused import errors
2024-03-07 15:23:45 -05:00
Karun Koppula
54751b7a50
Merge branch 'main' into karun/main_octospi_implementation
2024-03-07 15:20:29 -05:00
Karun
3b1d87050e
Update trait definitions
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Make operations generic against valid data widths
2024-03-07 14:41:27 -05:00
Karun
e163572bec
Add get and set config trait implementations
2024-03-07 14:41:26 -05:00
Karun
b86a1f0700
Add constructors
...
Add transfer configuration
Update command configuration
Add peripheral width consideration
Add drop impl
2024-03-07 14:41:04 -05:00
Karun
a0b7067205
Add user enums for transaction configuration
2024-03-07 14:30:53 -05:00
Karun
9ed8d01b11
Add transfer config, trait, functional initial configuration and read from memory
2024-03-07 14:30:53 -05:00
Karun
f3609f2842
Add initial octopsi module
2024-03-07 14:30:53 -05:00
Karun
9905bbe9f7
Update peripheral crate to updated octospi pac
2024-03-07 14:30:53 -05:00
Karun
2ab1b2ac9a
Update stm-32 build script to include ospi traits
2024-03-07 14:29:37 -05:00
Dario Nieuwenhuis
b2d236ee39
Merge pull request #2667 from timokroeger/stm32-anychannel-fix
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stm32: Implement `Channel` trait for `AnyChannel`
2024-03-07 15:18:32 +00:00
Tomas Barton
bb3711bbf9
update stm32c0 HSI frequency
2024-03-07 06:51:32 -08:00
Timo Kröger
bbc06458a3
stm32: Implement Channel trait for AnyChannel
2024-03-07 15:05:28 +01:00
Corey Schuhen
84d21e959d
Dummy
2024-03-07 17:45:01 +10:00
Corey Schuhen
98e7a0a423
Remove old PAC from bscan crate.
2024-03-07 17:45:01 +10:00
Corey Schuhen
9ba379fb9e
Remove usage of old PAC
...
Formatting
2024-03-07 17:45:01 +10:00
Corey Schuhen
65b38cf755
Fix examples and improve imports required.
2024-03-07 17:45:01 +10:00
Corey Schuhen
a9ff38003b
Documentation.
...
.
2024-03-07 17:45:01 +10:00
Corey Schuhen
455cc40261
Port registers access to using Embassy PAC
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Use stm32-metapac for filters module.
2024-03-07 17:45:01 +10:00
Corey Schuhen
b0f05e7682
Remove unused.
2024-03-07 17:45:01 +10:00
Corey Schuhen
34687a0956
Apply cargo fmt
...
Formatting.
2024-03-07 17:45:01 +10:00
Corey Schuhen
fecb65b988
Make use of internal BXCAN crate work. Tested on stm32f103 with real bus and HIL tests.
...
Fix
2024-03-07 17:45:01 +10:00
Corey Schuhen
f736f1b27f
RAW copy of files from BXCAN crate. No changes whatsoever.
2024-03-07 17:45:01 +10:00
Torin Cooper-Bennun
e0018c6f4f
stm32: can:fd: merge read impls; buffered RX returns Result<_, BusError>
2024-03-04 12:38:46 +00:00
Torin Cooper-Bennun
72c6cdc5d5
stm32: can: fd: rename TxBufferMode::Queue -> ::Priority for clarity
2024-03-04 12:22:18 +00:00
Dario Nieuwenhuis
ae266f3bf5
stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.
2024-03-04 00:08:14 +01:00
Dario Nieuwenhuis
c8c4b0b701
stm32/rcc: port g0 to new api.
2024-03-04 00:04:06 +01:00
Dario Nieuwenhuis
b4567bb8c5
stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.
2024-03-04 00:04:06 +01:00
Corey Schuhen
b693ab9b34
Restore init order to restore H7.
...
Previous commit broke H7 support in HIL farm. Restore previous order by moving a bunch of config from new and into_config_mode to apply_config.
This is a cleanup that I had considered to move more register access into peripheral.rs.
2024-03-02 14:18:12 +10:00
Corey Schuhen
bf06d10534
Delay setting TX buffer mode until user had a chance to configure it.
2024-03-02 14:00:56 +10:00
Torin Cooper-Bennun
9e403fa89a
stm32: can: fd: rename abort_pending_mailbox, rm pub qualifier
2024-03-02 10:08:20 +10:00
Torin Cooper-Bennun
befbb2845a
stm32: can: fd: write: if in TX FIFO mode & bufs full, then abort
2024-03-02 10:08:20 +10:00
Torin Cooper-Bennun
30606f9782
stm32: can: fd: allow TX buffers in FIFO mode
2024-03-02 10:08:20 +10:00
Dario Nieuwenhuis
3fe907b54d
Merge pull request #2646 from cschuhen/feature/wake_tx_on_buffered_push
...
Give CAN a kick when writing into TX buffer via sender.
2024-03-01 23:15:42 +00:00
Corey Schuhen
df8f508ffa
Writing to TX buffer also needs to fire an interrupt to kick off transmission if it is idle.
...
Formatting
2024-03-02 09:09:27 +10:00
Dario Nieuwenhuis
95234cddba
stm32: autogenerate mux config for all chips.
2024-03-01 23:54:37 +01:00
Dario Nieuwenhuis
d5c9c611fa
Merge pull request #2619 from caleb-garrett/cryp
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STM32 Crypto Accelerator
2024-03-01 19:35:57 +00:00
Siebe Claes
96af20cf5b
stm32: can: fd: Fix Frame is_extended() function
2024-03-01 19:21:01 +01:00
Caleb Garrett
c9cca3c007
Fix H7 CRYP operation.
2024-02-29 19:09:44 -05:00
Caleb Garrett
998532c33e
Merge branch 'embassy-rs:main' into cryp
2024-02-29 15:21:06 -05:00
Dario Nieuwenhuis
263d1b024c
Merge pull request #2637 from cschuhen/feature/fix_buf_size
...
Buffer is not big enough for FD frames.
2024-02-28 17:33:58 +00:00
eZio Pan
47c579eba2
update metapac
2024-02-29 00:11:40 +08:00
Corey Schuhen
1353a343b8
Buffer is not big enough for FD frames.
2024-02-28 18:03:53 +10:00
Dario Nieuwenhuis
5ced938184
Merge pull request #2634 from maiaherringfish/stm32h7-fdcansel-fix
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adding FDCANSEL logic for STM32H7x
2024-02-28 00:54:43 +00:00
Torin Cooper-Bennun
a8da42943f
stm32: can: fd: rm some irrelevant commented code and dead code
2024-02-27 23:47:41 +00:00
Torin Cooper-Bennun
0ed402fd79
stm32: can: fd: refactor out some duplicate code
2024-02-27 23:47:25 +00:00
Maia
b7e0964a07
added FDCANSEL logic for H7
2024-02-27 11:07:05 -08:00
Dario Nieuwenhuis
62c5df7e5b
Merge pull request #2631 from MaxiluxSystems/small-fdcan-fixes
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stm32: can: fd: fix SID read/write and BRS setting for TX
2024-02-27 12:19:03 +00:00
Torin Cooper-Bennun
9a4f58fe15
stm32: can: fd: only TX with BRS if also TXing with FDF
2024-02-27 10:38:40 +00:00
Torin Cooper-Bennun
e63b0d7a2f
stm32: can: fd: fix SID read/write from buf elems
2024-02-27 10:38:07 +00:00
eZio Pan
bf44adc4bc
allow higher psc value for iwdg_v3
2024-02-27 14:20:58 +08:00
Dario Nieuwenhuis
d5a2b3be58
Merge pull request #2614 from MaxiluxSystems/time_driver_tim1
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stm32: time_driver: allow use of TIM1 for driver
2024-02-26 12:08:32 +00:00
Torin Cooper-Bennun
5c45723777
stm32: timers: use TIMx_CC interrupt source for advanced timers
...
fixes (hopefully) time driver when using TIM1/8/20
2024-02-26 10:03:51 +00:00
Caleb Garrett
29d0d80808
Merge branch 'main' into cryp
2024-02-25 21:21:21 -05:00
Dario Nieuwenhuis
c83ab20526
stm32: update metapac.
2024-02-26 03:02:58 +01:00
Dario Nieuwenhuis
72c6f9a101
stm32/adc: reexport enums from PAC to avoid boilerplate hell.
2024-02-26 03:02:58 +01:00
Caleb Garrett
d9c0da8102
Update metapac to address CI build issue.
2024-02-25 20:59:07 -05:00
Caleb Garrett
236fc6f650
Add CRYP test.
2024-02-25 20:59:07 -05:00
Caleb Garrett
f352b6d68b
Address CI build issues.
2024-02-25 20:59:07 -05:00
Caleb Garrett
25ec838af5
Correct AAD ingest.
2024-02-25 20:59:07 -05:00
Caleb Garrett
967b4927b0
Correct tag generation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
cbca3a5c9f
Support v1 and v2 cryp variants.
2024-02-25 20:59:07 -05:00
Caleb Garrett
29d8b45956
Add DES and TDES support. Support variable tag sizes.
2024-02-25 20:59:07 -05:00
Caleb Garrett
14c2c28e06
Corrected additional associated data operation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
f64a62149e
Corrected CCM partial block ops.
2024-02-25 20:59:07 -05:00
Caleb Garrett
1e21b758f7
Corrected GCM tag generation.
2024-02-25 20:59:07 -05:00
Caleb Garrett
690b2118c6
CCM mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
fec26e8960
Refactored ciphers into traits.
2024-02-25 20:59:07 -05:00
Caleb Garrett
c2b03eff62
GCM mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
565acdf243
CTR mode functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
72e4cacd91
CBC and ECB AES modes functional.
2024-02-25 20:59:07 -05:00
Caleb Garrett
a0a8a4ec86
Support CBC, ECB, CTR modes.
2024-02-25 20:59:07 -05:00
Caleb Garrett
79e5e8b052
Add cryp configuration.
2024-02-25 20:59:07 -05:00
Dario Nieuwenhuis
a308b9ac2f
Merge branch 'adc_h5' into add-pll1_p_mul_2-clock
2024-02-26 02:14:38 +01:00
Eli Orona
abde7891e3
Update metapac version
2024-02-25 16:44:46 -08:00
Eli Orona
2dfd66b7c4
🤦
2024-02-25 16:25:42 -08:00
Eli Orona
7dbae799dc
Rust FMT
2024-02-25 16:24:52 -08:00
Eli Orona
c23b59bdc8
Add pll1_p_mul_2 clock.
2024-02-25 16:12:32 -08:00
Dario Nieuwenhuis
489d0be2a2
stm32/rcc: unify naming sysclk field to sys, enum to Sysclk.
2024-02-26 00:00:17 +01:00
Dario Nieuwenhuis
497515ed57
Merge pull request #2583 from OroArmor/tim_pll_clk
...
Enable PLL Clocks for TIMx peripherals on STM32F3xx Chips
2024-02-25 22:45:48 +00:00
Corey Schuhen
a737a7350e
FDCAN: Remove history from comments.
2024-02-25 10:14:12 +10:00
Corey Schuhen
1327a644b6
FDCAN: Don't require internal module for public API.
2024-02-25 10:14:12 +10:00
Corey Schuhen
0565098b06
FDCAN: Fix some indenting in macros
2024-02-25 10:14:12 +10:00
Corey Schuhen
a061cf3133
FDCAN: Allow access to buffered senders and receivers.
2024-02-25 10:14:12 +10:00
Corey Schuhen
779898c0e7
FDCAN: Expose some pub types in API
2024-02-25 10:14:12 +10:00
Corey Schuhen
2d634d07e0
FDCAN: Remove extra traits from.
...
Comments
Fix.
2024-02-25 10:13:58 +10:00
Eli Orona
394abda092
Fix report with the same name
2024-02-24 12:58:38 -08:00
Eli Orona
e79d2dd756
Move to internal mod and re-export the enums
2024-02-24 12:54:58 -08:00
Dario Nieuwenhuis
e67dfcb04f
stm32/dma: add AnyChannel, add support for BDMA on H7.
2024-02-24 02:41:41 +01:00
Torin Cooper-Bennun
86ccf0bc3e
stm32: remove TIM11 as time driver candidate (only 1 CC channel)
2024-02-23 14:35:12 +00:00
Torin Cooper-Bennun
44534abf32
stm32: sync available TIMs in Cargo.toml, build.rs
2024-02-23 14:35:12 +00:00
Torin Cooper-Bennun
a11e3146f8
stm32: time_driver: allow use of TIM1 for driver
2024-02-23 14:35:12 +00:00
Dario Nieuwenhuis
f77d59500e
Merge pull request #2618 from barnabywalters/g4rcc
...
[embassy-stm32] G4 RCC refactor amendments and additions
2024-02-23 13:05:01 +00:00
Barnaby Walters
b091ffcb55
[embassy-stm32] G4 RCC refactor amendments and additions
...
* Added assertions for a variety of clock frequencies, based on the reference manual and
stm32g474 datasheet. The family and numbers are consistent enough that I’m assuming
these numbers will work for the other chips.
* Corrected value of pll1_q in set_clocks call, added pll1_r value
2024-02-23 01:59:24 +01:00
Dario Nieuwenhuis
a6a5d9913c
Merge branch 'main' into stm32l0-reset-rtc
2024-02-23 01:45:10 +01:00
Dario Nieuwenhuis
0665e0d452
stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
2024-02-23 01:24:05 +01:00
Dario Nieuwenhuis
4481c5f3cc
Merge pull request #2616 from embassy-rs/h5-stupid-errata
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stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:25:30 +01:00
Dario Nieuwenhuis
475dea0208
stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:18:24 +01:00
Dario Nieuwenhuis
9c918f6474
Merge pull request #2588 from cschuhen/feature/fdcan_buffered
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Add FDCAN Buffered mode.
2024-02-23 00:07:05 +01:00
Torin Cooper-Bennun
5d2ccc8fa7
adc: basic H5 support
2024-02-22 15:50:13 +00:00
Eli Orona
88e29608ed
Rust fmt
2024-02-20 17:59:51 -08:00
Eli Orona
2ee9b37373
Move to a single Mux Struct.
2024-02-20 17:54:35 -08:00
Joonas Javanainen
9b2d096f4f
USB needs PWR_CR2 USV set on STM32L4
...
Confirmed to be needed on an STM32L422, and based on a quick look at
L4/L4+ reference manuals, this bit is present and required to be set on
all L4 chips that have some kind of USB peripheral (USB or OTG_FS).
The `usb_otg` driver already sets it for `cfg(stm32l4)` and we should do
the same thing here.
2024-02-20 21:47:13 +02:00
Dario Nieuwenhuis
55187c7276
Merge pull request #2602 from embassy-rs/peripheralref-no-derefmut
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hal-internal: remove impl DerefMut for PeripheralRef.
2024-02-20 13:51:01 +00:00
Dario Nieuwenhuis
e8474426d8
hal-internal: remove impl DerefMut for PeripheralRef.
...
if you have `PeripheralRef<'a, AnyPIn>` for pin A, and `AnyPin` (owned) for pin B, you can `mem::swap` them.
so, getting access forever to pin A, just by "sacrificing" pin B
this defeats the point of PeripheralRef, which is if you got a `PeripheralRef<'a, T>` then you're only allowed to use the peripheral for `'a`.
Also some drivers rely on the fact only one instance of a singleton exists for soundness, so this is a soundness fix for those.
2024-02-20 01:02:15 +01:00
Torin Cooper-Bennun
67230dc444
flash: h50: first pass at implementation
2024-02-19 16:05:50 +00:00
fe1es
5b7e2d8826
stm32/rcc: reset RTC on stm32l0
2024-02-19 15:25:24 +09:00
Corey Schuhen
eafa90cd07
Remove the OperatingMode typestates
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Instead have two explcit types(without the mode generic arg)types:
- One for config
- One for all operating modes
2024-02-18 13:09:37 +10:00
Zach
dd9f0d9d9e
support u5 flash
2024-02-17 12:04:53 -06:00
Corey Schuhen
5ad291b708
Add a buffered mode.
2024-02-17 18:26:57 +10:00
Corey Schuhen
91c75c92a0
Clean up and prep for buffered IRQ mode.
...
- Reduce code duplicaiton in read/write methods
- General clean-up
- Prepare for buffered mode
2024-02-17 18:26:57 +10:00
Corey Schuhen
5d8c54fdea
Move error conversion to peripheral.rs
2024-02-17 18:25:58 +10:00
Corey Schuhen
200ace566f
Don't use word Standard for frame format because it can be confused with ID format. Use Classic instead to mean CAN 2.0B frames.
2024-02-17 18:25:58 +10:00
Corey Schuhen
70b3c4374d
Port FDCAN HAL to use PAC directly instead of fdcan crate.
...
- Provide separate FDCAN capable and Classic CAN API's
- Don't use fdcan crate dep anymore
- Provide embedded-can traits.
2024-02-17 18:25:58 +10:00
Eli Orona
e99ef49611
Move to auto-generated based system.
2024-02-16 19:57:00 -08:00
Dario Nieuwenhuis
a3f508e6d1
Merge pull request #2570 from eZioPan/time-driver-singleton
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Add missing TIM for time-driver; reorder time-driver selection when use "time-drvier-any"
2024-02-17 02:34:45 +00:00
Eli Orona
c99c4a01a9
Update f013.rs
2024-02-16 16:47:38 -08:00
Eli Orona
7592e8be6e
Fix build
2024-02-16 16:45:58 -08:00
Eli Orona
77739faaeb
Rustfmt
2024-02-16 16:42:19 -08:00
Eli Orona
370db9fb06
Update f013.rs
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Add stm32f398
2024-02-16 16:39:23 -08:00
Dario Nieuwenhuis
9352621058
Merge pull request #2579 from barnabywalters/g4rcc
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[embassy-stm32]: stm32g4 RCC refactor
2024-02-16 23:38:49 +00:00
Barnaby Walters
6d7458dac7
Refinements
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* Implemented boost mode dance (RM0440 p234-245, 6.5.1)
* Enabled boost mode in usb_serial example, tested on hardware
* Removed hard requirement of a valid 48MHz source (HSI48 is checked if
requested, PLL passed through as-is and assumed to be valid)
* Used calc_pclk to calculate APB frequencies
* Refactored 48MHz configuration code to remove unnecessary let and block
* Renamed ahb_freq to hclk for clarity and consistency
2024-02-17 00:30:16 +01:00
Barnaby Walters
a24087c36c
Configured SYSCLK after boost mode, added comments
2024-02-16 21:52:58 +01:00
Barnaby Walters
e465dacf73
Added documentation, fixed and refined boost and flash read latency config
2024-02-16 21:34:12 +01:00
Barnaby Walters
25a95503f6
Configured HSI48 if enabled, assert is enabled if chosen as clk48 source
2024-02-16 20:41:04 +01:00
Barnaby Walters
ae74833999
Removed redundant HSI48 configuration
2024-02-16 20:32:35 +01:00
Barnaby Walters
32e4c93954
Removed dangling doc comments
2024-02-16 19:58:19 +01:00
Eli Orona
d7623c7929
Remove extraneous , in cfg
2024-02-15 23:20:35 -08:00
Eli Orona
d28ba1d606
rustfmt
2024-02-15 23:16:17 -08:00
Eli Orona
56b345c722
Clean up register setting
2024-02-15 23:12:18 -08:00
Eli Orona
4408c169a5
Fix cfg lines
2024-02-15 22:55:11 -08:00
Eli Orona
029d6383b5
Rust fmt and fix build.
2024-02-15 20:02:25 -08:00
Eli Orona
169f1ce928
I believe that this enables the PLL clock input to different TIMs for the STM32F3xx Series of chips.
2024-02-15 19:50:42 -08:00
Dario Nieuwenhuis
ae02467434
stm32: update metapac.
2024-02-16 02:07:21 +01:00
Barnaby Walters
396041ad1a
Commented out currently unused constants
2024-02-16 00:04:35 +01:00
Barnaby Walters
5b7eff6541
[embassy-stm32]: started stm32g4 RCC refactor
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* Copied API from f.rs where applicable
* HSE and HSI independantly configurable
* Boost mode set by user rather
* Added HSE, pll1_q and pll1_p frequencies to set_clocks call
* Stubbed max module based on f.rs, needs cleanup
2024-02-15 23:56:26 +01:00
Dario Nieuwenhuis
5220453d85
Merge pull request #2564 from embassy-rs/rcc-f1-update
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stm32/rcc: port F1, F0 to new API.
2024-02-14 16:40:11 +00:00
Dario Nieuwenhuis
1860e22693
stm32/rcc: unify f0, f1, f3.
2024-02-14 17:24:20 +01:00
eZio Pan
bbe1eebc53
Add missing TIM for time-driver; reorder time-driver selection when use "time-drvier-any".
2024-02-14 17:43:46 +08:00
Michael de Silva
0ceb313b6f
FIX: Correct typo in stm32 gpio
2024-02-14 07:22:52 +05:30
Caleb Garrett
14a678fe45
Fixed HMAC blocking mode.
2024-02-12 20:33:04 -05:00
Caleb Garrett
d8b4922b3c
Add STM32 HMAC function.
2024-02-12 20:33:04 -05:00
Dario Nieuwenhuis
8c82d1bcbc
Merge pull request #2528 from caleb-garrett/hash
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STM32 Hash Accelerator
2024-02-13 01:36:11 +01:00
Dario Nieuwenhuis
ccd2c574c3
stm32/rcc: port F0 to new API.
2024-02-13 01:21:51 +01:00
Dario Nieuwenhuis
b7c147445a
stm32/rcc: port F1 to new API.
2024-02-13 01:21:51 +01:00
Dario Nieuwenhuis
739c69bd63
stm32/rcc: some f3 fixes.
2024-02-13 01:15:54 +01:00
Dario Nieuwenhuis
937a9e7955
stm32/rcc: use h7 sdlevel enum from pac.
2024-02-12 20:58:04 +01:00
Dario Nieuwenhuis
0dc5e6d3e4
stm32/rcc: port F3 RCC to new API
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See #2515
2024-02-12 02:19:31 +01:00
Caleb Garrett
eb64d71247
Consolidated hash drivers.
2024-02-11 11:32:29 -05:00
eZio Pan
b4399a1bf5
timer-doc-fix
2024-02-10 16:22:36 +08:00
Dario Nieuwenhuis
832776d2c7
stm32: update metapac.
2024-02-10 02:50:35 +01:00
Caleb Garrett
0c9661a661
Merge branch 'main' into hash
2024-02-09 19:24:19 -05:00
eZio Pan
8fd803a5fe
use cfg_if to reduce macro condition
2024-02-10 00:00:43 +01:00
eZio Pan
0f94006be3
doc fix
2024-02-10 00:00:43 +01:00
eZio Pan
6c690ab259
restore original public API of timer, but keep new PAC
2024-02-10 00:00:43 +01:00
eZio Pan
b3cdf3a040
bug fix
2024-02-10 00:00:43 +01:00
eZio Pan
319f10da5d
stm32-timer: filter out c0, f1 and f37x
2024-02-10 00:00:43 +01:00
eZio Pan
5b646bc3bd
stm32-timer: L0 is special
2024-02-10 00:00:43 +01:00
eZio Pan
d538829f2f
add methods with macro
2024-02-10 00:00:43 +01:00
Dario Nieuwenhuis
53bf0332e9
asdkf
2024-02-10 00:00:43 +01:00
eZio Pan
dc4898ca89
update timer mod after stm32-metapac timer_v2
2024-02-09 23:58:13 +01:00
eZio Pan
d6636ca116
minor fix
2024-02-09 23:57:09 +01:00
Dario Nieuwenhuis
04147b4147
Merge pull request #2544 from shufps/feat/adc-l0
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Feat/adc l0
2024-02-09 22:48:57 +00:00
Ulf Lilleengen
1641f8a27e
Merge pull request #2397 from tyler-gilbert/add-write-immediate-api-dma-ring-buffer
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Add write_immediate() function to STM32 DMA ringbufer API
2024-02-09 20:05:41 +00:00
Caleb Garrett
f6645750c9
Removed hash DMA from unsupported configs.
2024-02-08 17:24:27 -05:00
shufps
34c71b58cf
made adc example working with default clock configuration and switched in v1 to PCLK/2 per default
2024-02-08 11:28:53 +01:00
shufps
dabe48c3bd
fmt
2024-02-08 11:15:28 +01:00
shufps
8d0a9bbefb
clippy
2024-02-08 11:14:14 +01:00
shufps
ab8f25fd78
added support for ADC of L0s
2024-02-08 10:47:26 +01:00
Caleb Garrett
bfa67c2993
Fix digest interrupt enable.
2024-02-06 18:37:48 -05:00
Dario Nieuwenhuis
2c5426aa5c
Merge pull request #2539 from badrbouslikhin/stm32h7-flash-improvements
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fix(stm32h7/flash): enhance resilience to program sequence errors (pgserr)
2024-02-06 15:58:50 +00:00
Caleb Garrett
b7db75adff
Updated stm32-metapac.
2024-02-06 10:44:52 -05:00
Badr Bouslikhin
aab5da1d3b
fix(stm32h7/flash): enhance resilience to program sequence errors (pgserr)
2024-02-06 12:30:04 +01:00
Badr Bouslikhin
e72cc9fb24
fix(stm32/h7): use correct unit in vco clock check
2024-02-06 11:33:39 +01:00
Dario Nieuwenhuis
e25eb6ca59
Merge pull request #2529 from GrantM11235/buffered-uart-doc-links
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stm32/usart: Add doc links to buffered uarts
2024-02-04 23:29:27 +01:00
Caleb Garrett
e1f6f4b31d
Merge branch 'main' into hash
2024-02-04 17:24:11 -05:00
Caleb Garrett
059d8a8222
Merge commit '1f940bf9e868438090ea126eb2267f5e9325fbd4' into hash
2024-02-04 17:19:15 -05:00
Caleb Garrett
66f44b95d7
Addressed hash CI build issues.
2024-02-04 17:16:33 -05:00
Dario Nieuwenhuis
6c72638ed0
stm32/rcc: fix more build failures.
2024-02-04 22:47:29 +01:00
Dario Nieuwenhuis
e3fe08428f
stm32/rcc: fix build for some f0 and l4 chips.
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Fixes #2531
2024-02-04 22:07:17 +01:00
Grant Miller
87a52f5ead
stm32/usart: Add doc links to buffered uarts
2024-02-03 17:04:20 -06:00
Caleb Garrett
1f940bf9e8
Merge branch 'main' into hash
2024-02-03 17:28:20 -05:00
Caleb Garrett
72bbfec39d
Added hash DMA implementation.
2024-02-03 16:10:00 -05:00
Stefan Gehr
b9d0069671
correct spelling of the word "receive"
2024-02-03 14:56:31 +01:00
Dario Nieuwenhuis
9866847375
stm32: autogenerate clocks struct, enable mux for all chips.
2024-02-02 23:24:34 +01:00
Dario Nieuwenhuis
a099084bff
Merge pull request #2520 from Ecco/stm32wba-rcc-v3
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Migrate STM32WBA to RCCv3
2024-02-02 20:48:39 +00:00
Romain Goyet
92690d8590
Migrate STM32WBA to RCCv3
2024-02-02 14:12:26 -05:00
Dario Nieuwenhuis
e05c8e2f44
stm32/dac: use autogenerated RCC impls.
2024-02-01 23:47:30 +01:00
Caleb Garrett
1027530902
Added hash interrupts for async.
2024-02-01 17:27:25 -05:00
Dario Nieuwenhuis
e7d1119750
stm32: automatically use refcounting for rcc bits used multiple times.
2024-02-01 23:15:17 +01:00
Joonas Javanainen
7e0f287431
Fix ADC max frequency for F2
2024-02-01 21:58:36 +02:00
Joonas Javanainen
21024e8638
Fix F2 temperature sensor ADC channel
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On all F2 devices (F205/207/215/217) the sensor is connected to
ADC1_IN16, and is not shared with VBAT which is connected to ADC1_IN18.
2024-02-01 21:48:29 +02:00
Romain Goyet
aa767272a8
STM32WBA's high speed external clock has to run at 32 MHz
2024-02-01 13:42:48 -05:00
Caleb Garrett
1dbfa5ab72
Added hash v1/v2 configs.
2024-02-01 10:28:12 -05:00
Caleb Garrett
6e9ddd4626
Added hash module with blocking implementation. Included SHA256 example.
2024-01-31 21:21:36 -05:00
Dario Nieuwenhuis
7e02389995
Merge pull request #2410 from eZioPan/waveform-on-CHx
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impl waveform with TIM OC Channel DMA
2024-02-01 01:02:01 +00:00
Dario Nieuwenhuis
e613324e16
stm32/eth: rename new_rmii to new, update metapac to fix issues with PC2_C.
2024-02-01 01:39:52 +01:00
Simon B. Gasse
42d8f3930a
Implement MII interface
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- Extend the eth/v2 module to support MII besides RMII.
- Replace `Ethernet::new` with `Ethernet::new_mii` and
`Ethernet::new_rmii`.
- Update ethernet examples.
- Add example for MII ethernet.
2024-02-01 01:33:34 +01:00
Corey Schuhen
1de78d0490
Initial FDCAN driver implementation.
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Original author:
Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Cleanup and documentaion by:
Tomasz bla Fortuna <bla@reactor.local>
Corey Schuhen <cschuhen@gmail.com>
Use new PAC method now that the names are common.
Use broken out definitions that can be shared with bxcan
Populate Rx struct with an embassy timestamp.
Remove use of RefCell.
As per review comment. - THis will probably get squashed down.
Fix
2024-01-31 05:40:05 +10:00
Tomasz bla Fortuna
03ba45065e
Add FDCAN clock registers to G4 RCC.
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Author: Adam Morgan <adam@luci.com>
Break definitions out of bxcan that can be used innm fdcan.
Typo
2024-01-31 05:40:05 +10:00
Tomasz bla Fortuna
a91a7a8557
Add FDCAN dependency in correct flavor based on selected chip.
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Author: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Change from review.
2024-01-31 05:40:05 +10:00
Dario Nieuwenhuis
5b2293e2b1
update stm32-metapac.
2024-01-30 02:34:12 +01:00
Dario Nieuwenhuis
3387ee7238
stm32/gpio: remove generics.
2024-01-22 21:31:06 +01:00
Dario Nieuwenhuis
43b6258a69
Merge pull request #2416 from andresv/stm32-fix-buffered-uart-flush
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stm32: fix buffered uart flush
2024-01-20 01:50:55 +00:00
Dario Nieuwenhuis
67159d80bb
Merge pull request #2429 from jr-oss/stm32_simple_pwm_add_set_output_compare_mode
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stm32/simple_pwm: add set_output_compare_mode
2024-01-20 01:33:49 +00:00
Dario Nieuwenhuis
326bff322e
Merge pull request #2415 from hdoordt/patch-1
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Make adc::Resolution::to_max_count const
2024-01-20 01:31:22 +00:00
Andres Vahter
ec2e3de0f4
stm32 uart: fix buffered flush for usart_v1, usart_v2
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There is one caveat. For some reason with first send using usart_v1/usart_v2 TC flag appears right after first byte from buffer is written to DR. Consecutive transfers work as expected - TC flag appears when last byte is fully transferred to wire.
2024-01-20 00:15:40 +01:00
Andres Vahter
534c53c901
stm32 uart: remove unwrap
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unwraps take more space because of panics
2024-01-20 00:15:40 +01:00
Andres Vahter
c936d66934
stm32 uart: fix flush for non usart_v4 variants
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Byte was written to TDR and right after that waker was called. This means `flush` would see that `tx_buf` is empty and can return Ready although actually hardware was still writing this last byte to the wire.
With this change non `usart_v4 ` variants would also use TC interrupt to check when last byte was sent out.
2024-01-20 00:15:39 +01:00
Andres Vahter
17d6e4eefe
stm32 uart: do not wake after sending each byte
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usart_v4 uses TC interrupt to see if all bytes are sent out from the FIFO and waker is called from this interrupt. This minimises unnecessary wakeups during sending.
2024-01-20 00:15:39 +01:00
Andres Vahter
ec47e931ac
stm32: fix buffered uart flush
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usart_v4 uses internal FIFO and therefore actually all bytes are not yet sent out although state.tx_buf.is_empty()
2024-01-20 00:15:39 +01:00
Harry Brooke
d781e231cd
make usart::State private
2024-01-19 23:20:20 +01:00
Dario Nieuwenhuis
9cd0beaee3
Merge pull request #2450 from shufps/feat/timer-driver-tim22-tim23
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adds timer-driver for tim21 and tim22 (on L0)
2024-01-15 12:01:22 +01:00
shufps
e969b88e5a
fixed trailing white spaces
2024-01-15 11:23:41 +01:00
