support u5 flash

This commit is contained in:
Zach 2024-02-17 12:04:53 -06:00
parent 377e58e408
commit dd9f0d9d9e
3 changed files with 162 additions and 1 deletions

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@ -101,10 +101,11 @@ pub enum FlashBank {
#[cfg_attr(any(flash_g0, flash_g4), path = "g.rs")]
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(flash_h7ab, path = "h7.rs")]
#[cfg_attr(flash_u5, path = "u5.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
flash_g4, flash_h7, flash_h7ab
flash_g4, flash_h7, flash_h7ab, flash_u5
)),
path = "other.rs"
)]

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@ -0,0 +1,105 @@
use core::convert::TryInto;
use core::ptr::write_volatile;
use core::sync::atomic::{fence, Ordering};
use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub(crate) const fn is_default_layout() -> bool {
true
}
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
pac::FLASH.seccr().modify(|w| w.set_lock(true));
}
pub(crate) unsafe fn unlock() {
if pac::FLASH.seccr().read().lock() {
pac::FLASH.seckeyr().write_value(0x4567_0123);
pac::FLASH.seckeyr().write_value(0xCDEF_89AB);
}
}
pub(crate) unsafe fn enable_blocking_write() {
assert_eq!(0, WRITE_SIZE % 4);
pac::FLASH.seccr().write(|w| {
w.set_pg(pac::flash::vals::SeccrPg::B_0X1);
});
}
pub(crate) unsafe fn disable_blocking_write() {
pac::FLASH.seccr().write(|w| w.set_pg(pac::flash::vals::SeccrPg::B_0X0));
}
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
let mut address = start_address;
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
address += val.len() as u32;
// prevents parallelism errors
fence(Ordering::SeqCst);
}
blocking_wait_ready()
}
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
pac::FLASH.seccr().modify(|w| {
w.set_per(pac::flash::vals::SeccrPer::B_0X1);
w.set_pnb(sector.index_in_bank)
});
pac::FLASH.seccr().modify(|w| {
w.set_strt(true);
});
let ret: Result<(), Error> = blocking_wait_ready();
pac::FLASH
.seccr()
.modify(|w| w.set_per(pac::flash::vals::SeccrPer::B_0X0));
clear_all_err();
ret
}
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 1 to clear" bits.
pac::FLASH.secsr().modify(|_| {});
}
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.secsr().read();
if !sr.bsy() {
if sr.pgserr() {
return Err(Error::Seq);
}
if sr.sizerr() {
return Err(Error::Size);
}
if sr.pgaerr() {
return Err(Error::Unaligned);
}
if sr.wrperr() {
return Err(Error::Protected);
}
if sr.progerr() {
return Err(Error::Prog);
}
return Ok(());
}
}
}

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@ -0,0 +1,55 @@
#![no_std]
#![no_main]
use defmt::{info, unwrap};
use embassy_executor::Spawner;
use embassy_stm32::flash::Flash;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello Flash!");
const ADDR: u32 = 0x8_0000; // This is the offset into the third region, the absolute address is 4x32K + 128K + 0x8_0000.
// wait a bit before accessing the flash
Timer::after_millis(300).await;
let mut f = Flash::new_blocking(p.FLASH).into_blocking_regions().bank1_region;
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.blocking_read(ADDR, &mut buf));
info!("Read: {=[u8]:x}", buf);
info!("Erasing...");
unwrap!(f.blocking_erase(ADDR, ADDR + 256 * 1024));
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.blocking_read(ADDR, &mut buf));
info!("Read after erase: {=[u8]:x}", buf);
info!("Writing...");
unwrap!(f.blocking_write(
ADDR,
&[
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31, 32
]
));
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.blocking_read(ADDR, &mut buf));
info!("Read: {=[u8]:x}", buf);
assert_eq!(
&buf[..],
&[
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31, 32
]
);
}