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support u5 flash
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377e58e408
commit
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@ -101,10 +101,11 @@ pub enum FlashBank {
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#[cfg_attr(any(flash_g0, flash_g4), path = "g.rs")]
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#[cfg_attr(flash_h7, path = "h7.rs")]
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#[cfg_attr(flash_h7ab, path = "h7.rs")]
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#[cfg_attr(flash_u5, path = "u5.rs")]
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#[cfg_attr(
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not(any(
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flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
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flash_g4, flash_h7, flash_h7ab
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flash_g4, flash_h7, flash_h7ab, flash_u5
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)),
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path = "other.rs"
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)]
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105
embassy-stm32/src/flash/u5.rs
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105
embassy-stm32/src/flash/u5.rs
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@ -0,0 +1,105 @@
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use core::convert::TryInto;
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use core::ptr::write_volatile;
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use core::sync::atomic::{fence, Ordering};
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use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
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use crate::flash::Error;
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use crate::pac;
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pub(crate) const fn is_default_layout() -> bool {
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true
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}
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pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
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&FLASH_REGIONS
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}
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pub(crate) unsafe fn lock() {
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pac::FLASH.seccr().modify(|w| w.set_lock(true));
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}
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pub(crate) unsafe fn unlock() {
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if pac::FLASH.seccr().read().lock() {
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pac::FLASH.seckeyr().write_value(0x4567_0123);
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pac::FLASH.seckeyr().write_value(0xCDEF_89AB);
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}
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}
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pub(crate) unsafe fn enable_blocking_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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pac::FLASH.seccr().write(|w| {
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w.set_pg(pac::flash::vals::SeccrPg::B_0X1);
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});
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}
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pub(crate) unsafe fn disable_blocking_write() {
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pac::FLASH.seccr().write(|w| w.set_pg(pac::flash::vals::SeccrPg::B_0X0));
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}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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// prevents parallelism errors
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fence(Ordering::SeqCst);
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}
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blocking_wait_ready()
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}
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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pac::FLASH.seccr().modify(|w| {
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w.set_per(pac::flash::vals::SeccrPer::B_0X1);
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w.set_pnb(sector.index_in_bank)
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});
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pac::FLASH.seccr().modify(|w| {
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w.set_strt(true);
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});
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let ret: Result<(), Error> = blocking_wait_ready();
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pac::FLASH
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.seccr()
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.modify(|w| w.set_per(pac::flash::vals::SeccrPer::B_0X0));
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clear_all_err();
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ret
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}
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pub(crate) unsafe fn clear_all_err() {
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// read and write back the same value.
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// This clears all "write 1 to clear" bits.
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pac::FLASH.secsr().modify(|_| {});
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}
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unsafe fn blocking_wait_ready() -> Result<(), Error> {
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loop {
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let sr = pac::FLASH.secsr().read();
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if !sr.bsy() {
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if sr.pgserr() {
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return Err(Error::Seq);
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}
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if sr.sizerr() {
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return Err(Error::Size);
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}
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if sr.pgaerr() {
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return Err(Error::Unaligned);
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}
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.progerr() {
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return Err(Error::Prog);
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}
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return Ok(());
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}
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}
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}
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55
examples/stm32u5/src/bin/flash.rs
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55
examples/stm32u5/src/bin/flash.rs
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@ -0,0 +1,55 @@
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#![no_std]
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#![no_main]
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use defmt::{info, unwrap};
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use embassy_executor::Spawner;
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use embassy_stm32::flash::Flash;
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use embassy_time::Timer;
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_stm32::init(Default::default());
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info!("Hello Flash!");
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const ADDR: u32 = 0x8_0000; // This is the offset into the third region, the absolute address is 4x32K + 128K + 0x8_0000.
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// wait a bit before accessing the flash
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Timer::after_millis(300).await;
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let mut f = Flash::new_blocking(p.FLASH).into_blocking_regions().bank1_region;
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info!("Reading...");
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let mut buf = [0u8; 32];
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unwrap!(f.blocking_read(ADDR, &mut buf));
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info!("Read: {=[u8]:x}", buf);
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info!("Erasing...");
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unwrap!(f.blocking_erase(ADDR, ADDR + 256 * 1024));
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info!("Reading...");
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let mut buf = [0u8; 32];
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unwrap!(f.blocking_read(ADDR, &mut buf));
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info!("Read after erase: {=[u8]:x}", buf);
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info!("Writing...");
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unwrap!(f.blocking_write(
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ADDR,
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&[
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
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30, 31, 32
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]
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));
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info!("Reading...");
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let mut buf = [0u8; 32];
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unwrap!(f.blocking_read(ADDR, &mut buf));
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info!("Read: {=[u8]:x}", buf);
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assert_eq!(
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&buf[..],
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&[
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
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30, 31, 32
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]
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);
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}
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