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Fix build
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77739faaeb
commit
7592e8be6e
@ -495,7 +495,7 @@ pub(crate) unsafe fn init(config: Config) {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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.modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
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}
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};
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@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
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stm32f398
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))]
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match config.tim.tim15 {
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TimClockSource::PClk2 => None,
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TimClockSource::PClk2 => {},
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
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stm32f398
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))]
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match config.tim.tim16 {
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TimClockSource::PClk2 => None,
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TimClockSource::PClk2 => {},
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
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stm32f398
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))]
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match config.tim.tim17 {
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TimClockSource::PClk2 => None,
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TimClockSource::PClk2 => {},
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
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#[cfg(any(all(stm32f303, any(package_D, package_E))))]
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match config.tim.tim20 {
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TimClockSource::PClk2 => None,
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TimClockSource::PClk2 => {},
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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