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https://github.com/embassy-rs/embassy.git
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Merge pull request #2564 from embassy-rs/rcc-f1-update
stm32/rcc: port F1, F0 to new API.
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
5220453d85
7
ci.sh
7
ci.sh
@ -88,6 +88,13 @@ cargo batch \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
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@ -68,7 +68,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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critical-section = "1.1"
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#stm32-metapac = { version = "15" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8" }
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vcell = "0.1.3"
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bxcan = "0.7.0"
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nb = "1.0.0"
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@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8", default-features = false, features = ["metadata"]}
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[features]
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@ -1,196 +0,0 @@
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use stm32_metapac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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/// Configuration of the clocks
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///
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/// hse takes precedence over hsi48 if both are enabled
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#[non_exhaustive]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub usb_pll: bool,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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pub sys_ck: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk: Option<Hertz>,
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pub ls: super::LsConfig,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hse: Default::default(),
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bypass_hse: Default::default(),
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usb_pll: Default::default(),
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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sys_ck: Default::default(),
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hclk: Default::default(),
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pclk: Default::default(),
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ls: Default::default(),
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI_FREQ.0);
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#[cfg(crs)]
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let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
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#[cfg(not(crs))]
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let hsi48: Option<Hertz> = None;
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let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
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if hsi48.is_some() {
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return (48_000_000, true);
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}
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(HSI_FREQ.0, false)
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});
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let (pllmul_bits, real_sysclk) = if sysclk == src_clk {
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(None, sysclk)
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} else {
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let prediv = if config.hse.is_some() { 1 } else { 2 };
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let pllmul = (2 * prediv * sysclk + src_clk) / src_clk / 2;
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let pllmul = pllmul.max(2).min(16);
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let pllmul_bits = pllmul as u8 - 2;
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let real_sysclk = pllmul * src_clk / prediv;
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(Some(pllmul_bits), real_sysclk)
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};
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let hpre_bits = config
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.hclk
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.map(|hclk| match real_sysclk / hclk.0 {
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0 => unreachable!(),
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1 => 0b0111,
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2 => 0b1000,
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3..=5 => 0b1001,
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6..=11 => 0b1010,
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12..=39 => 0b1011,
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40..=95 => 0b1100,
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96..=191 => 0b1101,
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192..=383 => 0b1110,
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_ => 0b1111,
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})
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.unwrap_or(0b0111);
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let hclk = real_sysclk / (1 << (hpre_bits - 0b0111));
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let ppre_bits = config
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.pclk
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.map(|pclk| match hclk / pclk.0 {
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0 => unreachable!(),
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1 => 0b011,
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2 => 0b100,
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3..=5 => 0b101,
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6..=11 => 0b110,
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_ => 0b111,
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})
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.unwrap_or(0b011);
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let ppre: u8 = 1 << (ppre_bits - 0b011);
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let pclk = hclk / u32::from(ppre);
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let timer_mul = if ppre == 1 { 1 } else { 2 };
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FLASH.acr().write(|w| {
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w.set_latency(if real_sysclk <= 24_000_000 {
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Latency::WS0
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} else {
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Latency::WS1
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});
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});
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match (config.hse.is_some(), use_hsi48) {
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(true, _) => {
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RCC.cr().modify(|w| {
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w.set_csson(true);
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w.set_hseon(true);
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w.set_hsebyp(config.bypass_hse);
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});
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while !RCC.cr().read().hserdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV))
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}
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}
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// use_hsi48 will always be false for stm32f0x0
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#[cfg(not(stm32f0x0))]
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(false, true) => {
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RCC.cr2().modify(|w| w.set_hsi48on(true));
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while !RCC.cr2().read().hsi48rdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
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}
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}
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_ => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI_DIV2))
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}
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}
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}
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if config.usb_pll {
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RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
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}
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// TODO: Option to use CRS (Clock Recovery)
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if let Some(pllmul_bits) = pllmul_bits {
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RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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w.set_sw(Sw::PLL1_P)
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});
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} else {
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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if config.hse.is_some() {
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w.set_sw(Sw::HSE);
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} else if use_hsi48 {
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#[cfg(not(stm32f0x0))]
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w.set_sw(Sw::HSI48);
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} else {
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w.set_sw(Sw::HSI)
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}
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})
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}
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let rtc = config.ls.init();
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set_clocks!(
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hsi: None,
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lse: None,
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sys: Some(Hertz(real_sysclk)),
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pclk1: Some(Hertz(pclk)),
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pclk2: Some(Hertz(pclk)),
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pclk1_tim: Some(Hertz(pclk * timer_mul)),
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pclk2_tim: Some(Hertz(pclk * timer_mul)),
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hclk1: Some(Hertz(hclk)),
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rtc: rtc,
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hsi48: hsi48,
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// TODO:
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pll1_p: None,
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);
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}
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@ -1,9 +1,14 @@
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use crate::pac::flash::vals::Latency;
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pub use crate::pac::rcc::vals::{
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Adcpres as AdcPllPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv,
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Sw as Sysclk,
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};
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use crate::pac::rcc::vals::{Pllsrc, Usbpre};
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#[cfg(stm32f1)]
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pub use crate::pac::rcc::vals::Adcpre as ADCPrescaler;
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#[cfg(stm32f3)]
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pub use crate::pac::rcc::vals::Adcpres as AdcPllPrescaler;
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use crate::pac::rcc::vals::Pllsrc;
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#[cfg(stm32f1)]
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pub use crate::pac::rcc::vals::Pllxtpre as PllPreDiv;
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#[cfg(any(stm32f0, stm32f3))]
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pub use crate::pac::rcc::vals::Prediv as PllPreDiv;
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Sw as Sysclk};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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@ -30,6 +35,8 @@ pub struct Hse {
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pub enum PllSource {
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HSE,
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HSI,
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#[cfg(rcc_f0v4)]
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HSI48,
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}
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#[derive(Clone, Copy)]
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@ -38,19 +45,21 @@ pub struct Pll {
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/// PLL pre-divider.
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///
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/// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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/// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy)]
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pub enum AdcClockSource {
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Pll(AdcPllPrescaler),
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Hclk(AdcHclkPrescaler),
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum AdcHclkPrescaler {
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Div1,
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@ -58,6 +67,7 @@ pub enum AdcHclkPrescaler {
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Div4,
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}
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#[cfg(stm32f334)]
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum HrtimClockSource {
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BusClk,
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@ -69,17 +79,23 @@ pub enum HrtimClockSource {
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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pub sys: Sysclk,
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pub pll: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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#[cfg(not(stm32f0))]
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pub apb2_pre: APBPrescaler,
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#[cfg(not(rcc_f37))]
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#[cfg(stm32f1)]
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pub adc_pre: ADCPrescaler,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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pub adc: AdcClockSource,
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#[cfg(all(not(rcc_f37), adc3_common))]
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#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
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pub adc34: AdcClockSource,
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#[cfg(stm32f334)]
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pub hrtim: HrtimClockSource,
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@ -92,16 +108,24 @@ impl Default for Config {
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Self {
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hsi: true,
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hse: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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sys: Sysclk::HSI,
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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#[cfg(not(stm32f0))]
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apb2_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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#[cfg(not(rcc_f37))]
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#[cfg(stm32f1)]
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// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
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adc_pre: ADCPrescaler::DIV6,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(all(not(rcc_f37), adc3_common))]
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#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
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adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(stm32f334)]
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hrtim: HrtimClockSource::BusClk,
|
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@ -143,13 +167,18 @@ pub(crate) unsafe fn init(config: Config) {
|
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}
|
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};
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// configure HSI48
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#[cfg(crs)]
|
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let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
|
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#[cfg(not(crs))]
|
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let hsi48: Option<Hertz> = None;
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|
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// Enable PLL
|
||||
// RM0316: "Reserved, must be kept at reset value."
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let pll = config.pll.map(|pll| {
|
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let (src_val, src_freq) = match pll.src {
|
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#[cfg(rcc_f3v3)]
|
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#[cfg(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))]
|
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PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
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#[cfg(not(rcc_f3v3))]
|
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#[cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3)))]
|
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PllSource::HSI => {
|
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if pll.prediv != PllPreDiv::DIV2 {
|
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panic!("if PLL source is HSI, PLL prediv must be 2.");
|
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@ -157,16 +186,21 @@ pub(crate) unsafe fn init(config: Config) {
|
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(Pllsrc::HSI_DIV2, unwrap!(hsi))
|
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}
|
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PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
|
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#[cfg(rcc_f0v4)]
|
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PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
|
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};
|
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let in_freq = src_freq / pll.prediv;
|
||||
assert!(max::PLL_IN.contains(&in_freq));
|
||||
let out_freq = in_freq * pll.mul;
|
||||
assert!(max::PLL_OUT.contains(&out_freq));
|
||||
|
||||
#[cfg(not(stm32f1))]
|
||||
RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_pllmul(pll.mul);
|
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w.set_pllsrc(src_val);
|
||||
#[cfg(stm32f1)]
|
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w.set_pllxtpre(pll.prediv);
|
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});
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
@ -174,17 +208,16 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
out_freq
|
||||
});
|
||||
|
||||
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
|
||||
let usb = match pll {
|
||||
Some(Hertz(72_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
Some(Hertz(48_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
|
||||
Some(Hertz(48_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1),
|
||||
_ => None,
|
||||
};
|
||||
}
|
||||
.map(|usbpre| {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(usbpre));
|
||||
Hertz(48_000_000)
|
||||
});
|
||||
|
||||
// Configure sysclk
|
||||
let sys = match config.sys {
|
||||
@ -196,13 +229,28 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
|
||||
let hclk = sys / config.ahb_pre;
|
||||
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
|
||||
#[cfg(not(stm32f0))]
|
||||
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
|
||||
#[cfg(stm32f0)]
|
||||
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
|
||||
|
||||
assert!(max::HCLK.contains(&hclk));
|
||||
assert!(max::PCLK1.contains(&pclk1));
|
||||
#[cfg(not(stm32f0))]
|
||||
assert!(max::PCLK2.contains(&pclk2));
|
||||
|
||||
#[cfg(stm32f1)]
|
||||
let adc = pclk2 / config.adc_pre;
|
||||
#[cfg(stm32f1)]
|
||||
assert!(max::ADC.contains(&adc));
|
||||
|
||||
// Set latency based on HCLK frquency
|
||||
#[cfg(stm32f0)]
|
||||
let latency = match hclk.0 {
|
||||
..=24_000_000 => Latency::WS0,
|
||||
_ => Latency::WS1,
|
||||
};
|
||||
#[cfg(any(stm32f1, stm32f3))]
|
||||
let latency = match hclk.0 {
|
||||
..=24_000_000 => Latency::WS0,
|
||||
..=48_000_000 => Latency::WS1,
|
||||
@ -213,18 +261,28 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
// RM0316: "The prefetch buffer must be kept on when using a prescaler
|
||||
// different from 1 on the AHB clock.", "Half-cycle access cannot be
|
||||
// used when there is a prescaler different from 1 on the AHB clock"
|
||||
#[cfg(stm32f3)]
|
||||
if config.ahb_pre != AHBPrescaler::DIV1 {
|
||||
w.set_hlfcya(false);
|
||||
w.set_prftbe(true);
|
||||
}
|
||||
#[cfg(not(stm32f3))]
|
||||
w.set_prftbe(true);
|
||||
});
|
||||
|
||||
// Set prescalers
|
||||
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_ppre2(config.apb1_pre);
|
||||
w.set_ppre1(config.apb2_pre);
|
||||
RCC.cfgr().modify(|w: &mut stm32_metapac::rcc::regs::Cfgr| {
|
||||
#[cfg(not(stm32f0))]
|
||||
{
|
||||
w.set_ppre1(config.apb1_pre);
|
||||
w.set_ppre2(config.apb2_pre);
|
||||
}
|
||||
#[cfg(stm32f0)]
|
||||
w.set_ppre(config.apb1_pre);
|
||||
w.set_hpre(config.ahb_pre);
|
||||
#[cfg(stm32f1)]
|
||||
w.set_adcpre(config.adc_pre);
|
||||
});
|
||||
|
||||
// Wait for the new prescalers to kick in
|
||||
@ -234,13 +292,14 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
|
||||
// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| w.set_sw(config.sys));
|
||||
while RCC.cfgr().read().sws() != config.sys {}
|
||||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
use crate::pac::adccommon::vals::Ckmode;
|
||||
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
let adc = match config.adc {
|
||||
AdcClockSource::Pll(adcpres) => {
|
||||
RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
|
||||
@ -264,7 +323,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
}
|
||||
};
|
||||
|
||||
#[cfg(all(not(rcc_f37), adc3_common))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
|
||||
let adc34 = match config.adc34 {
|
||||
AdcClockSource::Pll(adcpres) => {
|
||||
RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
|
||||
@ -315,18 +374,63 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
pclk1_tim: Some(pclk1_tim),
|
||||
pclk2_tim: Some(pclk2_tim),
|
||||
hclk1: Some(hclk),
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
adc: Some(adc),
|
||||
#[cfg(all(not(rcc_f37), adc3_common))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
|
||||
adc34: Some(adc34),
|
||||
#[cfg(stm32f334)]
|
||||
hrtim: hrtim,
|
||||
rtc: rtc,
|
||||
hsi48: hsi48,
|
||||
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
|
||||
usb: usb,
|
||||
lse: None,
|
||||
);
|
||||
}
|
||||
|
||||
#[cfg(stm32f0)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
|
||||
}
|
||||
|
||||
#[cfg(stm32f1)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
|
||||
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
|
||||
}
|
||||
|
||||
#[cfg(stm32f3)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
@ -1,191 +0,0 @@
|
||||
use core::convert::TryFrom;
|
||||
|
||||
use crate::pac::flash::vals::Latency;
|
||||
use crate::pac::rcc::vals::*;
|
||||
use crate::pac::{FLASH, RCC};
|
||||
use crate::time::Hertz;
|
||||
|
||||
/// HSI speed
|
||||
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
|
||||
|
||||
/// Configuration of the clocks
|
||||
///
|
||||
#[non_exhaustive]
|
||||
#[derive(Default)]
|
||||
pub struct Config {
|
||||
pub hse: Option<Hertz>,
|
||||
|
||||
pub sys_ck: Option<Hertz>,
|
||||
pub hclk: Option<Hertz>,
|
||||
pub pclk1: Option<Hertz>,
|
||||
pub pclk2: Option<Hertz>,
|
||||
pub adcclk: Option<Hertz>,
|
||||
pub pllxtpre: bool,
|
||||
|
||||
pub ls: super::LsConfig,
|
||||
}
|
||||
|
||||
pub(crate) unsafe fn init(config: Config) {
|
||||
let pllxtpre_div = if config.pllxtpre { 2 } else { 1 };
|
||||
let pllsrcclk = config.hse.map(|hse| hse.0 / pllxtpre_div).unwrap_or(HSI_FREQ.0 / 2);
|
||||
|
||||
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
|
||||
let pllmul = sysclk / pllsrcclk;
|
||||
|
||||
let (pllmul_bits, real_sysclk) = if pllmul == 1 {
|
||||
(None, config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0))
|
||||
} else {
|
||||
let pllmul = core::cmp::min(core::cmp::max(pllmul, 1), 16);
|
||||
(Some(pllmul as u8 - 2), pllsrcclk * pllmul)
|
||||
};
|
||||
|
||||
assert!(real_sysclk <= 72_000_000);
|
||||
|
||||
let hpre_bits = config
|
||||
.hclk
|
||||
.map(|hclk| match real_sysclk / hclk.0 {
|
||||
0 => unreachable!(),
|
||||
1 => 0b0111,
|
||||
2 => 0b1000,
|
||||
3..=5 => 0b1001,
|
||||
6..=11 => 0b1010,
|
||||
12..=39 => 0b1011,
|
||||
40..=95 => 0b1100,
|
||||
96..=191 => 0b1101,
|
||||
192..=383 => 0b1110,
|
||||
_ => 0b1111,
|
||||
})
|
||||
.unwrap_or(0b0111);
|
||||
|
||||
let hclk = if hpre_bits >= 0b1100 {
|
||||
real_sysclk / (1 << (hpre_bits - 0b0110))
|
||||
} else {
|
||||
real_sysclk / (1 << (hpre_bits - 0b0111))
|
||||
};
|
||||
|
||||
assert!(hclk <= 72_000_000);
|
||||
|
||||
let ppre1_bits = config
|
||||
.pclk1
|
||||
.map(|pclk1| match hclk / pclk1.0 {
|
||||
0 => unreachable!(),
|
||||
1 => 0b011,
|
||||
2 => 0b100,
|
||||
3..=5 => 0b101,
|
||||
6..=11 => 0b110,
|
||||
_ => 0b111,
|
||||
})
|
||||
.unwrap_or(0b011);
|
||||
|
||||
let ppre1 = 1 << (ppre1_bits - 0b011);
|
||||
let pclk1 = hclk / u32::try_from(ppre1).unwrap();
|
||||
let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
|
||||
|
||||
assert!(pclk1 <= 36_000_000);
|
||||
|
||||
let ppre2_bits = config
|
||||
.pclk2
|
||||
.map(|pclk2| match hclk / pclk2.0 {
|
||||
0 => unreachable!(),
|
||||
1 => 0b011,
|
||||
2 => 0b100,
|
||||
3..=5 => 0b101,
|
||||
6..=11 => 0b110,
|
||||
_ => 0b111,
|
||||
})
|
||||
.unwrap_or(0b011);
|
||||
|
||||
let ppre2 = 1 << (ppre2_bits - 0b011);
|
||||
let pclk2 = hclk / u32::try_from(ppre2).unwrap();
|
||||
let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
|
||||
|
||||
assert!(pclk2 <= 72_000_000);
|
||||
|
||||
FLASH.acr().write(|w| {
|
||||
w.set_latency(if real_sysclk <= 24_000_000 {
|
||||
Latency::WS0
|
||||
} else if real_sysclk <= 48_000_000 {
|
||||
Latency::WS1
|
||||
} else {
|
||||
Latency::WS2
|
||||
});
|
||||
// the prefetch buffer is enabled by default, let's keep it enabled
|
||||
w.set_prftbe(true);
|
||||
});
|
||||
|
||||
// the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
|
||||
// PLL output frequency is a supported one.
|
||||
// usbpre == false: divide clock by 1.5, otherwise no division
|
||||
#[cfg(not(rcc_f100))]
|
||||
let (usbpre, _usbclk_valid) = match (config.hse, pllmul_bits, real_sysclk) {
|
||||
(Some(_), Some(_), 72_000_000) => (false, true),
|
||||
(Some(_), Some(_), 48_000_000) => (true, true),
|
||||
_ => (true, false),
|
||||
};
|
||||
|
||||
let apre_bits: u8 = config
|
||||
.adcclk
|
||||
.map(|adcclk| match pclk2 / adcclk.0 {
|
||||
0..=2 => 0b00,
|
||||
3..=4 => 0b01,
|
||||
5..=7 => 0b10,
|
||||
_ => 0b11,
|
||||
})
|
||||
.unwrap_or(0b11);
|
||||
|
||||
let apre = (apre_bits + 1) << 1;
|
||||
let adcclk = pclk2 / unwrap!(u32::try_from(apre));
|
||||
|
||||
assert!(adcclk <= 14_000_000);
|
||||
|
||||
if config.hse.is_some() {
|
||||
// enable HSE and wait for it to be ready
|
||||
RCC.cr().modify(|w| w.set_hseon(true));
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
}
|
||||
|
||||
if let Some(pllmul_bits) = pllmul_bits {
|
||||
let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
|
||||
RCC.cfgr()
|
||||
.modify(|w| w.set_pllxtpre(Pllxtpre::from_bits(pllctpre_flag)));
|
||||
|
||||
// enable PLL and wait for it to be ready
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_pllmul(Pllmul::from_bits(pllmul_bits));
|
||||
w.set_pllsrc(Pllsrc::from_bits(config.hse.is_some() as u8));
|
||||
});
|
||||
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
}
|
||||
|
||||
// Only needed for stm32f103?
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_adcpre(Adcpre::from_bits(apre_bits));
|
||||
w.set_ppre2(Ppre::from_bits(ppre2_bits));
|
||||
w.set_ppre1(Ppre::from_bits(ppre1_bits));
|
||||
w.set_hpre(Hpre::from_bits(hpre_bits));
|
||||
#[cfg(not(rcc_f100))]
|
||||
w.set_usbpre(Usbpre::from_bits(usbpre as u8));
|
||||
w.set_sw(if pllmul_bits.is_some() {
|
||||
Sw::PLL1_P
|
||||
} else if config.hse.is_some() {
|
||||
Sw::HSE
|
||||
} else {
|
||||
Sw::HSI
|
||||
});
|
||||
});
|
||||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
set_clocks!(
|
||||
sys: Some(Hertz(real_sysclk)),
|
||||
pclk1: Some(Hertz(pclk1)),
|
||||
pclk2: Some(Hertz(pclk2)),
|
||||
pclk1_tim: Some(Hertz(pclk1 * timer_mul1)),
|
||||
pclk2_tim: Some(Hertz(pclk2 * timer_mul2)),
|
||||
hclk1: Some(Hertz(hclk)),
|
||||
adc: Some(Hertz(adcclk)),
|
||||
rtc: rtc,
|
||||
);
|
||||
}
|
||||
@ -4,7 +4,7 @@ use embassy_hal_internal::into_ref;
|
||||
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::Speed;
|
||||
#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
|
||||
#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
|
||||
pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
|
||||
#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
|
||||
pub use crate::pac::rcc::vals::Mcosel as McoSource;
|
||||
@ -13,7 +13,7 @@ pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
|
||||
use crate::pac::RCC;
|
||||
use crate::{peripherals, Peripheral};
|
||||
|
||||
#[cfg(any(stm32f1, rcc_f3v1, rcc_f37))]
|
||||
#[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
|
||||
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
|
||||
pub enum McoPrescaler {
|
||||
DIV1,
|
||||
@ -43,7 +43,7 @@ macro_rules! impl_peri {
|
||||
|
||||
r.modify(|w| {
|
||||
w.$set_source(source);
|
||||
#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
|
||||
#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
|
||||
w.$set_prescaler(_prescaler);
|
||||
});
|
||||
}
|
||||
|
||||
@ -18,17 +18,15 @@ mod hsi48;
|
||||
#[cfg(crs)]
|
||||
pub use hsi48::*;
|
||||
|
||||
#[cfg_attr(rcc_f0, path = "f0.rs")]
|
||||
#[cfg_attr(any(stm32f1), path = "f1.rs")]
|
||||
#[cfg_attr(any(stm32f3), path = "f3.rs")]
|
||||
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
|
||||
#[cfg_attr(rcc_c0, path = "c0.rs")]
|
||||
#[cfg_attr(rcc_g0, path = "g0.rs")]
|
||||
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
||||
#[cfg_attr(any(stm32f0, stm32f1, stm32f3), path = "f013.rs")]
|
||||
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f247.rs")]
|
||||
#[cfg_attr(stm32c0, path = "c0.rs")]
|
||||
#[cfg_attr(stm32g0, path = "g0.rs")]
|
||||
#[cfg_attr(stm32g4, path = "g4.rs")]
|
||||
#[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
|
||||
#[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
|
||||
#[cfg_attr(rcc_u5, path = "u5.rs")]
|
||||
#[cfg_attr(rcc_wba, path = "wba.rs")]
|
||||
#[cfg_attr(stm32u5, path = "u5.rs")]
|
||||
#[cfg_attr(stm32wba, path = "wba.rs")]
|
||||
mod _version;
|
||||
|
||||
pub use _version::*;
|
||||
|
||||
@ -3,15 +3,13 @@
|
||||
|
||||
use defmt::info;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::Config;
|
||||
use embassy_time::Timer;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) -> ! {
|
||||
let mut config = Config::default();
|
||||
config.rcc.sys_ck = Some(Hertz(36_000_000));
|
||||
let config = Config::default();
|
||||
let _p = embassy_stm32::init(config);
|
||||
|
||||
loop {
|
||||
|
||||
@ -21,9 +21,23 @@ bind_interrupts!(struct Irqs {
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.rcc.hse = Some(Hertz(8_000_000));
|
||||
config.rcc.sys_ck = Some(Hertz(48_000_000));
|
||||
config.rcc.pclk1 = Some(Hertz(24_000_000));
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
// Oscillator for bluepill, Bypass for nucleos.
|
||||
mode: HseMode::Oscillator,
|
||||
});
|
||||
config.rcc.pll = Some(Pll {
|
||||
src: PllSource::HSE,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL9,
|
||||
});
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV2;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV1;
|
||||
}
|
||||
let mut p = embassy_stm32::init(config);
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
@ -14,9 +14,9 @@ rustflags = [
|
||||
]
|
||||
|
||||
[build]
|
||||
target = "thumbv6m-none-eabi"
|
||||
#target = "thumbv6m-none-eabi"
|
||||
#target = "thumbv7m-none-eabi"
|
||||
#target = "thumbv7em-none-eabi"
|
||||
target = "thumbv7em-none-eabi"
|
||||
#target = "thumbv8m.main-none-eabihf"
|
||||
|
||||
[env]
|
||||
|
||||
@ -247,6 +247,24 @@ pub fn config() -> Config {
|
||||
config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f103c8")]
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::Oscillator,
|
||||
});
|
||||
config.rcc.pll = Some(Pll {
|
||||
src: PllSource::HSE,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL9,
|
||||
});
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV2;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV1;
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f207zg")]
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user