elagil
edb9b03dee
fix: flush SAI FIFO on init
2024-11-15 00:07:23 +01:00
elagil
4692f06c33
fix: flush SAI FIFO on disable
2024-11-15 00:01:40 +01:00
Dario Nieuwenhuis
796f6c034a
Release embassy-executor 0.6.3.
2024-11-12 18:07:50 +01:00
Junfeng Liu
4d75c4ee51
Fix wrong unit
2024-11-12 10:36:44 +08:00
Dario Nieuwenhuis
0de204ccd7
Fix "non-local impl definition" warning from recent nightlies.
2024-11-08 13:20:13 +01:00
Christian Enderle
cf2424f5c2
RCC: add lsi and lse clock frequency for STM32U5
2024-11-07 14:16:10 +01:00
Christian Enderle
7231032f97
RCC: added msik for stm32u5
2024-11-07 13:32:07 +01:00
elagil
e69be0a23b
fix: STM32U5 RCC fields
2024-11-06 19:46:55 +01:00
elagil
555231aeb5
chore: update stm32 data source
2024-11-06 19:46:52 +01:00
Dario Nieuwenhuis
dbba791795
Merge pull request #3500 from KennethKnudsen97/main
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Add split_ref for stm32 uart
2024-11-06 17:08:16 +00:00
Dániel Buga
94659325ab
Prep executor 0.6.2
2024-11-06 13:58:02 +01:00
Kenneth Knudsen
72109a7bda
Split_ref with shortened lifetime. When borrowed skip drop on rx and tx
2024-11-06 10:52:03 +01:00
Kenneth Knudsen
aa453caa79
add split_ref for stm32 uart
2024-11-04 15:08:57 +01:00
Dario Nieuwenhuis
089b8a482e
Merge pull request #3451 from dvdsk/read_ready
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stm32/uart impl ReadReady for RingbufferdUart
2024-11-03 23:57:07 +00:00
Christian Enderle
926ae1a1d5
low-power: add support for stm32u5
2024-11-03 10:56:40 +01:00
dvdsk
43ff5a9b28
stm32/uart fix leftover DmaUnsynced public api
2024-11-02 14:00:27 +01:00
Krzysztof Królczyk
e93ac532ac
feat/stm32: disable multicast filtering on eth v2
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Initially, this was feature-gated, but has been requested
to be changed to be unconditional, see PR 3488 for reasons.
When filtering is enabled, it intercepts and drops silently
ipv6 packets, possibly somewhere around
smoltcp::iface::interface::ipv6 lines 36, 44 in current head
sha e9b66eadaeacef758ebc4a12378f8d2162144cf4
With filtering disabled (this patch), packets are received
and communication over ipv6 is possible, neighbor discovery works.
related: #2496
Signed-off-by: Krzysztof Królczyk <Krzysztof.Krolczyk@o2.pl>
2024-11-01 19:02:10 +01:00
Dario Nieuwenhuis
04bd2bac76
Merge pull request #3475 from diondokter/qspi-async
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STM32 Qspi async
2024-10-30 09:57:09 +00:00
Dion Dokter
a3bbb3b43a
Add check for the flipside of the coin too
2024-10-29 23:35:28 +01:00
Dion Dokter
9fdfe5e99b
Fix typo
2024-10-29 17:50:46 +01:00
Dion Dokter
2d899a17e7
Add some sanity checks
2024-10-29 17:26:35 +01:00
Dion Dokter
5db6b4874d
Expose async functions for QSPI
2024-10-29 17:13:09 +01:00
Dario Nieuwenhuis
10c9fbcc99
Merge pull request #3458 from williams-one/fix-ltdc-settings-for-stm32u5
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Fix LTDC registry settings for STM32U5
2024-10-29 10:45:31 +00:00
Dario Nieuwenhuis
1457e4d1ac
Merge pull request #3456 from HaoboGu/feat/ospi_mm
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Add memory mapped mode for stm32 ospi
2024-10-27 18:24:13 +00:00
Dario Nieuwenhuis
f0a2616dd6
Merge pull request #3468 from korken89/fix-can-hang
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This fixes 2 issues where STM32 BXCAN would hang
2024-10-27 18:19:56 +00:00
Emil Fresk
917f1d1f4d
This fixes 2 issues where STM32 BXCAN would hang
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1. If one received frames under an `interrupt_free` section, in my case
`init` in RTIC, the RX IRQ will fire and clear it's enable bit after
`interrupt_free` is complete. There is no frame to read so RX is now
unconditionally disabled forever.
2. On clearing of RX IRQ, TX stops silently. This happens due to the use
of `write` instead of `modify` when modifying IRQ enable bits.
Solution 1: Enable RX IRQs on every call to `try_read` that return no
data. This solution also solves the issue of very delayed handling of
the RX IRQ which would cause the same issue.
Solution 2: Use `modify` instead of `write`.
2024-10-27 10:10:46 +01:00
Haobo Gu
ca6bcb4250
feat(ospi): add ospi example
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Signed-off-by: Haobo Gu <haobogu@outlook.com>
2024-10-26 23:41:46 +08:00
dvdsk
edac7cc630
stm32/uart remove DmaUnsynced from public api
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Its an internal error which should never be exposed. It should only
occur with wrong driver implementations. We log to the user and return
an Overrun error since handling DmaUnsynced as an Overrun will resolve it.
2024-10-26 12:38:10 +02:00
William
45e7a7a55a
Update CFBLR configuration
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As per section "43.7.23 LTDC layer x color frame buffer length register (LTDC_LxCFBLR)" of Reference manual for STM32U5 RM0456, CFBLL has to be set to the length of one pixel line plus 3 (instead of plus 7 as for H7)
2024-10-25 15:03:26 +02:00
Haobo Gu
7b62d70d18
feat(ospi): add memory mapped mode
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Signed-off-by: Haobo Gu <haobogu@outlook.com>
2024-10-25 18:27:48 +08:00
dvdsk
be50b62677
stm32/uart impl ReadReady for RingbufferdUart
2024-10-23 21:06:58 +02:00
Ulf Lilleengen
8803128707
Merge pull request #3317 from GrantM11235/simplepwmchannel
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embassy-stm32: Add SimplePwmChannel
2024-10-23 10:30:13 +00:00
Haobo Gu
e5bc266654
feat: set ospi memory mapped mode
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Signed-off-by: Haobo Gu <haobogu@outlook.com>
2024-10-23 12:54:50 +08:00
Dario Nieuwenhuis
8eb80c6816
Merge pull request #3444 from dnbln/main
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feat: allow `bind_interrupts!` to accept conditional compilation attrs
2024-10-22 15:18:35 +00:00
Dinu Blanovschi
c797915525
fix: review comments
2024-10-22 16:56:05 +02:00
Dinu Blanovschi
e9f2e63796
fix
2024-10-22 16:50:10 +02:00
Dinu Blanovschi
5c23c789ee
fix
2024-10-22 16:23:17 +02:00
Dinu Blanovschi
82a438a037
fix
2024-10-22 15:51:05 +02:00
Dinu Blanovschi
ccd635f0dc
fix + allow both conditions on the irq and the handlers
2024-10-22 15:43:28 +02:00
Dinu Blanovschi
3279c19eee
feat(stm32): allow bind_interrupts! to accept conditional compilation attrs
2024-10-22 12:30:37 +02:00
Lucas Martins
82772e3a8f
📝 fix wrong comment
2024-10-21 17:50:05 -03:00
Lucas Martins
2c9b528edd
fmt
2024-10-21 15:06:06 -03:00
Lucas Martins
c0addc005b
add uart permutations usefull for rs485
2024-10-21 14:48:57 -03:00
Lucas Martins
1d395fc2b6
stm32/flash: add stm32f2, stm32h5 flash driver
2024-10-21 02:21:53 +02:00
Dario Nieuwenhuis
34eeaa0787
Merge pull request #3435 from embassy-rs/octospim-fix
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stm32: Fix build for chips with octospim but not octospi2.
2024-10-20 23:37:47 +00:00
Dario Nieuwenhuis
ecac24a1c7
stm32: Fix build for chips with octospim but not octospi2.
2024-10-21 01:30:21 +02:00
Dario Nieuwenhuis
1a24b4f018
Release embassy-executor v0.6.1, embassy-executor-macros v0.6.1
2024-10-21 01:26:02 +02:00
Christian Enderle
9cf75d7eac
stm32/flash: add support for l5
2024-10-17 20:17:01 +02:00
Alexandros Liarokapis
9f1b6b4791
Revise I2S interface to ring-buffered.
2024-10-16 18:45:27 +03:00
Tu Nguyen
8af52488e7
add RTR flag if it is remote frame
2024-10-16 17:45:40 +07:00
