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Merge pull request #3475 from diondokter/qspi-async

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STM32 Qspi async
This commit is contained in:
Dario Nieuwenhuis 2024-10-30 09:57:09 +00:00 committed by GitHub
commit 04bd2bac76
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1 changed files with 43 additions and 4 deletions
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47
embassy-stm32/src/qspi/mod.rs
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@ -202,6 +202,21 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
}
fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig, data_len: Option<usize>) {
match (transaction.address, transaction.awidth) {
(Some(_), QspiWidth::NONE) => panic!("QSPI address can't be sent with an address width of NONE"),
(Some(_), _) => {}
(None, QspiWidth::NONE) => {}
(None, _) => panic!("QSPI address is not set, so the address width should be NONE"),
}
match (data_len, transaction.dwidth) {
(Some(0), _) => panic!("QSPI data must be at least one byte"),
(Some(_), QspiWidth::NONE) => panic!("QSPI data can't be sent with a data width of NONE"),
(Some(_), _) => {}
(None, QspiWidth::NONE) => {}
(None, _) => panic!("QSPI data is empty, so the data width should be NONE"),
}
T::REGS.fcr().modify(|v| {
v.set_csmf(true);
v.set_ctcf(true);
@ -353,6 +368,21 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
/// Blocking read data, using DMA.
pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
let transfer = self.start_read_transfer(transaction, buf);
transfer.blocking_wait();
}
/// Async read data, using DMA.
pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
let transfer = self.start_read_transfer(transaction, buf);
transfer.await;
}
fn start_read_transfer<'a>(
&'a mut self,
transaction: TransferConfig,
buf: &'a mut [u8],
) -> crate::dma::Transfer<'a> {
self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
T::REGS.ccr().modify(|v| {
@ -373,12 +403,22 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer.blocking_wait();
transfer
}
/// Blocking write data, using DMA.
pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
let transfer = self.start_write_transfer(transaction, buf);
transfer.blocking_wait();
}
/// Async write data, using DMA.
pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
let transfer = self.start_write_transfer(transaction, buf);
transfer.await;
}
fn start_write_transfer<'a>(&'a mut self, transaction: TransferConfig, buf: &'a [u8]) -> crate::dma::Transfer<'a> {
self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
T::REGS.ccr().modify(|v| {
@ -395,8 +435,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer.blocking_wait();
transfer
}
}