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https://github.com/embassy-rs/embassy.git
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Merge pull request #3456 from HaoboGu/feat/ospi_mm
Add memory mapped mode for stm32 ospi
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
1457e4d1ac
1
ci.sh
1
ci.sh
@ -216,6 +216,7 @@ cargo batch \
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--- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32g4 \
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--- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/stm32h5 \
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--- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h7 \
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--- build --release --manifest-path examples/stm32h7b0/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h7b0 \
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--- build --release --manifest-path examples/stm32h735/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h735 \
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--- build --release --manifest-path examples/stm32h755cm4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h755cm4 \
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--- build --release --manifest-path examples/stm32h755cm7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h755cm7 \
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@ -179,6 +179,71 @@ pub struct Ospi<'d, T: Instance, M: PeriMode> {
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}
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impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
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/// Enter memory mode.
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/// The Input `read_config` is used to configure the read operation in memory mode
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pub fn enable_memory_mapped_mode(
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&mut self,
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read_config: TransferConfig,
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write_config: TransferConfig,
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) -> Result<(), OspiError> {
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// Use configure command to set read config
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self.configure_command(&read_config, None)?;
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let reg = T::REGS;
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while reg.sr().read().busy() {}
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reg.ccr().modify(|r| {
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r.set_dqse(false);
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r.set_sioo(true);
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});
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// Set wrting configurations, there are separate registers for write configurations in memory mapped mode
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reg.wccr().modify(|w| {
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w.set_imode(PhaseMode::from_bits(write_config.iwidth.into()));
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w.set_idtr(write_config.idtr);
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w.set_isize(SizeInBits::from_bits(write_config.isize.into()));
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w.set_admode(PhaseMode::from_bits(write_config.adwidth.into()));
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w.set_addtr(write_config.idtr);
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w.set_adsize(SizeInBits::from_bits(write_config.adsize.into()));
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w.set_dmode(PhaseMode::from_bits(write_config.dwidth.into()));
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w.set_ddtr(write_config.ddtr);
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w.set_abmode(PhaseMode::from_bits(write_config.abwidth.into()));
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w.set_dqse(true);
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});
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reg.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
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// Enable memory mapped mode
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reg.cr().modify(|r| {
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r.set_fmode(crate::ospi::vals::FunctionalMode::MEMORYMAPPED);
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r.set_tcen(false);
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});
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Ok(())
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}
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/// Quit from memory mapped mode
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pub fn disable_memory_mapped_mode(&mut self) {
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let reg = T::REGS;
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reg.cr().modify(|r| {
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r.set_fmode(crate::ospi::vals::FunctionalMode::INDIRECTWRITE);
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r.set_abort(true);
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r.set_dmaen(false);
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r.set_en(false);
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});
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// Clear transfer complete flag
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reg.fcr().write(|w| w.set_ctcf(true));
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// Re-enable ospi
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reg.cr().modify(|r| {
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r.set_en(true);
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});
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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8
examples/stm32h7b0/.cargo/config.toml
Normal file
8
examples/stm32h7b0/.cargo/config.toml
Normal file
@ -0,0 +1,8 @@
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[target.thumbv7em-none-eabihf]
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runner = 'probe-rs run --chip STM32H7B0VBTx'
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[build]
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target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
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[env]
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DEFMT_LOG = "trace"
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74
examples/stm32h7b0/Cargo.toml
Normal file
74
examples/stm32h7b0/Cargo.toml
Normal file
@ -0,0 +1,74 @@
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[package]
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edition = "2021"
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name = "embassy-stm32h7b0-examples"
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version = "0.1.0"
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license = "MIT OR Apache-2.0"
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[dependencies]
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32h7b0vb", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
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embassy-sync = { version = "0.6.0", path = "../../embassy-sync", features = ["defmt"] }
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embassy-embedded-hal = { version = "0.2.0", path = "../../embassy-embedded-hal" }
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embassy-executor = { version = "0.6.1", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
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embassy-time = { version = "0.3.2", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
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embassy-net = { version = "0.4.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
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embassy-usb = { version = "0.3.0", path = "../../embassy-usb", features = ["defmt"] }
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embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
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defmt = "0.3"
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defmt-rtt = "0.4"
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cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
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cortex-m-rt = "0.7.0"
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embedded-hal = "0.2.6"
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embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
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embedded-hal-async = { version = "1.0" }
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embedded-nal-async = "0.8.0"
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embedded-io-async = { version = "0.6.1" }
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panic-probe = { version = "0.3", features = ["print-defmt"] }
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heapless = { version = "0.8", default-features = false }
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rand_core = "0.6.3"
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critical-section = "1.1"
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micromath = "2.0.0"
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stm32-fmc = "0.3.0"
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embedded-storage = "0.3.1"
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static_cell = "2"
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chrono = { version = "^0.4", default-features = false }
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grounded = "0.2.0"
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# cargo build/run
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[profile.dev]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 3 # <-
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overflow-checks = true # <-
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# cargo test
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[profile.test]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 3 # <-
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overflow-checks = true # <-
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# cargo build/run --release
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[profile.release]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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# cargo test --release
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[profile.bench]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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35
examples/stm32h7b0/build.rs
Normal file
35
examples/stm32h7b0/build.rs
Normal file
@ -0,0 +1,35 @@
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//! This build script copies the `memory.x` file from the crate root into
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//! a directory where the linker can always find it at build time.
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//! For many projects this is optional, as the linker always searches the
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//! project root directory -- wherever `Cargo.toml` is. However, if you
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//! are using a workspace or have a more complicated build setup, this
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//! build script becomes required. Additionally, by requesting that
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//! Cargo re-run the build script whenever `memory.x` is changed,
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//! updating `memory.x` ensures a rebuild of the application with the
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//! new memory settings.
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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// Put `memory.x` in our output directory and ensure it's
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// on the linker search path.
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(include_bytes!("memory.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// By default, Cargo will re-run a build script whenever
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// any file in the project changes. By specifying `memory.x`
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// here, we ensure the build script is only re-run when
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// `memory.x` is changed.
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println!("cargo:rerun-if-changed=memory.x");
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println!("cargo:rustc-link-arg-bins=--nmagic");
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println!("cargo:rustc-link-arg-bins=-Tlink.x");
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println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
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}
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5
examples/stm32h7b0/memory.x
Normal file
5
examples/stm32h7b0/memory.x
Normal file
@ -0,0 +1,5 @@
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MEMORY
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{
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FLASH : ORIGIN = 0x08000000, LENGTH = 128K /* BANK_1 */
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RAM : ORIGIN = 0x24000000, LENGTH = 512K /* SRAM */
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}
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433
examples/stm32h7b0/src/bin/ospi_memory_mapped.rs
Normal file
433
examples/stm32h7b0/src/bin/ospi_memory_mapped.rs
Normal file
@ -0,0 +1,433 @@
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#![no_main]
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#![no_std]
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// Tested on weact stm32h7b0 board + w25q64 spi flash
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use defmt::info;
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use embassy_executor::Spawner;
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use embassy_stm32::gpio::{Level, Output, Speed};
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use embassy_stm32::mode::Blocking;
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use embassy_stm32::ospi::{
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AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, Instance, MemorySize, MemoryType, Ospi,
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OspiWidth, TransferConfig, WrapSize,
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};
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use embassy_stm32::time::Hertz;
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use embassy_stm32::Config;
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use embassy_time::Timer;
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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// RCC config
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let mut config = Config::default();
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info!("START");
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{
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use embassy_stm32::rcc::*;
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config.rcc.hsi = Some(HSIPrescaler::DIV1);
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config.rcc.csi = true;
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// Needed for USB
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config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true });
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// External oscillator 25MHZ
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config.rcc.hse = Some(Hse {
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freq: Hertz(25_000_000),
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mode: HseMode::Oscillator,
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});
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config.rcc.pll1 = Some(Pll {
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source: PllSource::HSE,
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prediv: PllPreDiv::DIV5,
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mul: PllMul::MUL112,
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divp: Some(PllDiv::DIV2),
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divq: Some(PllDiv::DIV2),
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divr: Some(PllDiv::DIV2),
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});
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config.rcc.sys = Sysclk::PLL1_P;
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config.rcc.ahb_pre = AHBPrescaler::DIV2;
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config.rcc.apb1_pre = APBPrescaler::DIV2;
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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config.rcc.apb3_pre = APBPrescaler::DIV2;
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config.rcc.apb4_pre = APBPrescaler::DIV2;
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config.rcc.voltage_scale = VoltageScale::Scale0;
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}
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// Initialize peripherals
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let p = embassy_stm32::init(config);
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let qspi_config = embassy_stm32::ospi::Config {
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fifo_threshold: FIFOThresholdLevel::_16Bytes,
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memory_type: MemoryType::Micron,
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device_size: MemorySize::_8MiB,
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chip_select_high_time: ChipSelectHighTime::_1Cycle,
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free_running_clock: false,
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clock_mode: false,
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wrap_size: WrapSize::None,
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clock_prescaler: 4,
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sample_shifting: true,
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delay_hold_quarter_cycle: false,
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chip_select_boundary: 0,
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delay_block_bypass: true,
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max_transfer: 0,
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refresh: 0,
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};
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let ospi = embassy_stm32::ospi::Ospi::new_blocking_quadspi(
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p.OCTOSPI1,
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p.PB2,
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p.PD11,
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p.PD12,
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p.PE2,
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p.PD13,
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p.PB6,
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qspi_config,
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);
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let mut flash = FlashMemory::new(ospi).await;
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let flash_id = flash.read_id();
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info!("FLASH ID: {=[u8]:x}", flash_id);
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let mut wr_buf = [0u8; 8];
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for i in 0..8 {
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wr_buf[i] = i as u8;
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}
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let mut rd_buf = [0u8; 8];
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flash.erase_sector(0).await;
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flash.write_memory(0, &wr_buf, true).await;
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flash.read_memory(0, &mut rd_buf, true);
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info!("WRITE BUF: {=[u8]:#X}", wr_buf);
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info!("READ BUF: {=[u8]:#X}", rd_buf);
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flash.enable_mm().await;
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info!("Enabled memory mapped mode");
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let first_u32 = unsafe { *(0x90000000 as *const u32) };
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assert_eq!(first_u32, 0x03020100);
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let second_u32 = unsafe { *(0x90000004 as *const u32) };
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assert_eq!(second_u32, 0x07060504);
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flash.disable_mm().await;
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info!("DONE");
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// Output pin PE3
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let mut led = Output::new(p.PE3, Level::Low, Speed::Low);
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loop {
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led.toggle();
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Timer::after_millis(1000).await;
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}
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}
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const MEMORY_PAGE_SIZE: usize = 8;
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const CMD_QUAD_READ: u8 = 0x6B;
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const CMD_QUAD_WRITE_PG: u8 = 0x32;
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const CMD_READ_ID: u8 = 0x9F;
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const CMD_ENABLE_RESET: u8 = 0x66;
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const CMD_RESET: u8 = 0x99;
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const CMD_WRITE_ENABLE: u8 = 0x06;
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const CMD_CHIP_ERASE: u8 = 0xC7;
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const CMD_SECTOR_ERASE: u8 = 0x20;
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const CMD_BLOCK_ERASE_32K: u8 = 0x52;
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const CMD_BLOCK_ERASE_64K: u8 = 0xD8;
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const CMD_READ_SR: u8 = 0x05;
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const CMD_READ_CR: u8 = 0x35;
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const CMD_WRITE_SR: u8 = 0x01;
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const CMD_WRITE_CR: u8 = 0x31;
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/// Implementation of access to flash chip.
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/// Chip commands are hardcoded as it depends on used chip.
|
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/// This implementation is using chip GD25Q64C from Giga Device
|
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pub struct FlashMemory<I: Instance> {
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ospi: Ospi<'static, I, Blocking>,
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}
|
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|
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impl<I: Instance> FlashMemory<I> {
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pub async fn new(ospi: Ospi<'static, I, Blocking>) -> Self {
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let mut memory = Self { ospi };
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||||
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memory.reset_memory().await;
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memory.enable_quad();
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memory
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||||
}
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||||
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async fn qpi_mode(&mut self) {
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// Enter qpi mode
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self.exec_command(0x38).await;
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|
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// Set read param
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let transaction = TransferConfig {
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iwidth: OspiWidth::QUAD,
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dwidth: OspiWidth::QUAD,
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instruction: Some(0xC0),
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..Default::default()
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};
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self.enable_write().await;
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self.ospi.blocking_write(&[0x30_u8], transaction).unwrap();
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self.wait_write_finish();
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}
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pub async fn disable_mm(&mut self) {
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self.ospi.disable_memory_mapped_mode();
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}
|
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pub async fn enable_mm(&mut self) {
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self.qpi_mode().await;
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let read_config = TransferConfig {
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iwidth: OspiWidth::QUAD,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::QUAD,
|
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::QUAD,
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instruction: Some(0x0B), // Fast read in QPI mode
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dummy: DummyCycles::_8,
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..Default::default()
|
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};
|
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let write_config = TransferConfig {
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iwidth: OspiWidth::SING,
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||||
isize: AddressSize::_8Bit,
|
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adwidth: OspiWidth::SING,
|
||||
adsize: AddressSize::_24bit,
|
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dwidth: OspiWidth::QUAD,
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instruction: Some(0x32), // Write config
|
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dummy: DummyCycles::_0,
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..Default::default()
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};
|
||||
self.ospi.enable_memory_mapped_mode(read_config, write_config).unwrap();
|
||||
}
|
||||
|
||||
fn enable_quad(&mut self) {
|
||||
let cr = self.read_cr();
|
||||
// info!("Read cr: {:x}", cr);
|
||||
self.write_cr(cr | 0x02);
|
||||
// info!("Read cr after writing: {:x}", cr);
|
||||
}
|
||||
|
||||
pub fn disable_quad(&mut self) {
|
||||
let cr = self.read_cr();
|
||||
self.write_cr(cr & (!(0x02)));
|
||||
}
|
||||
|
||||
async fn exec_command_4(&mut self, cmd: u8) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: OspiWidth::QUAD,
|
||||
adwidth: OspiWidth::NONE,
|
||||
// adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::NONE,
|
||||
instruction: Some(cmd as u32),
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
self.ospi.command(&transaction).await.unwrap();
|
||||
}
|
||||
|
||||
async fn exec_command(&mut self, cmd: u8) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
adwidth: OspiWidth::NONE,
|
||||
// adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::NONE,
|
||||
instruction: Some(cmd as u32),
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
// info!("Excuting command: {:x}", transaction.instruction);
|
||||
self.ospi.command(&transaction).await.unwrap();
|
||||
}
|
||||
|
||||
pub async fn reset_memory(&mut self) {
|
||||
self.exec_command_4(CMD_ENABLE_RESET).await;
|
||||
self.exec_command_4(CMD_RESET).await;
|
||||
self.exec_command(CMD_ENABLE_RESET).await;
|
||||
self.exec_command(CMD_RESET).await;
|
||||
self.wait_write_finish();
|
||||
}
|
||||
|
||||
pub async fn enable_write(&mut self) {
|
||||
self.exec_command(CMD_WRITE_ENABLE).await;
|
||||
}
|
||||
|
||||
pub fn read_id(&mut self) -> [u8; 3] {
|
||||
let mut buffer = [0; 3];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
isize: AddressSize::_8Bit,
|
||||
adwidth: OspiWidth::NONE,
|
||||
// adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::SING,
|
||||
instruction: Some(CMD_READ_ID as u32),
|
||||
..Default::default()
|
||||
};
|
||||
// info!("Reading id: 0x{:X}", transaction.instruction);
|
||||
self.ospi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
buffer
|
||||
}
|
||||
|
||||
pub fn read_id_4(&mut self) -> [u8; 3] {
|
||||
let mut buffer = [0; 3];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
isize: AddressSize::_8Bit,
|
||||
adwidth: OspiWidth::NONE,
|
||||
dwidth: OspiWidth::QUAD,
|
||||
instruction: Some(CMD_READ_ID as u32),
|
||||
..Default::default()
|
||||
};
|
||||
info!("Reading id: 0x{:X}", transaction.instruction);
|
||||
self.ospi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
buffer
|
||||
}
|
||||
|
||||
pub fn read_memory(&mut self, addr: u32, buffer: &mut [u8], use_dma: bool) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
adwidth: OspiWidth::SING,
|
||||
adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::QUAD,
|
||||
instruction: Some(CMD_QUAD_READ as u32),
|
||||
address: Some(addr),
|
||||
dummy: DummyCycles::_8,
|
||||
..Default::default()
|
||||
};
|
||||
if use_dma {
|
||||
self.ospi.blocking_read(buffer, transaction).unwrap();
|
||||
} else {
|
||||
self.ospi.blocking_read(buffer, transaction).unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
fn wait_write_finish(&mut self) {
|
||||
while (self.read_sr() & 0x01) != 0 {}
|
||||
}
|
||||
|
||||
async fn perform_erase(&mut self, addr: u32, cmd: u8) {
|
||||
let transaction = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
adwidth: OspiWidth::SING,
|
||||
adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::NONE,
|
||||
instruction: Some(cmd as u32),
|
||||
address: Some(addr),
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
self.enable_write().await;
|
||||
self.ospi.command(&transaction).await.unwrap();
|
||||
self.wait_write_finish();
|
||||
}
|
||||
|
||||
pub async fn erase_sector(&mut self, addr: u32) {
|
||||
self.perform_erase(addr, CMD_SECTOR_ERASE).await;
|
||||
}
|
||||
|
||||
pub async fn erase_block_32k(&mut self, addr: u32) {
|
||||
self.perform_erase(addr, CMD_BLOCK_ERASE_32K).await;
|
||||
}
|
||||
|
||||
pub async fn erase_block_64k(&mut self, addr: u32) {
|
||||
self.perform_erase(addr, CMD_BLOCK_ERASE_64K).await;
|
||||
}
|
||||
|
||||
pub async fn erase_chip(&mut self) {
|
||||
self.exec_command(CMD_CHIP_ERASE).await;
|
||||
}
|
||||
|
||||
async fn write_page(&mut self, addr: u32, buffer: &[u8], len: usize, use_dma: bool) {
|
||||
assert!(
|
||||
(len as u32 + (addr & 0x000000ff)) <= MEMORY_PAGE_SIZE as u32,
|
||||
"write_page(): page write length exceeds page boundary (len = {}, addr = {:X}",
|
||||
len,
|
||||
addr
|
||||
);
|
||||
|
||||
let transaction = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
adsize: AddressSize::_24bit,
|
||||
adwidth: OspiWidth::SING,
|
||||
dwidth: OspiWidth::QUAD,
|
||||
instruction: Some(CMD_QUAD_WRITE_PG as u32),
|
||||
address: Some(addr),
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
self.enable_write().await;
|
||||
if use_dma {
|
||||
self.ospi.blocking_write(buffer, transaction).unwrap();
|
||||
} else {
|
||||
self.ospi.blocking_write(buffer, transaction).unwrap();
|
||||
}
|
||||
self.wait_write_finish();
|
||||
}
|
||||
|
||||
pub async fn write_memory(&mut self, addr: u32, buffer: &[u8], use_dma: bool) {
|
||||
let mut left = buffer.len();
|
||||
let mut place = addr;
|
||||
let mut chunk_start = 0;
|
||||
|
||||
while left > 0 {
|
||||
let max_chunk_size = MEMORY_PAGE_SIZE - (place & 0x000000ff) as usize;
|
||||
let chunk_size = if left >= max_chunk_size { max_chunk_size } else { left };
|
||||
let chunk = &buffer[chunk_start..(chunk_start + chunk_size)];
|
||||
self.write_page(place, chunk, chunk_size, use_dma).await;
|
||||
place += chunk_size as u32;
|
||||
left -= chunk_size;
|
||||
chunk_start += chunk_size;
|
||||
}
|
||||
}
|
||||
|
||||
fn read_register(&mut self, cmd: u8) -> u8 {
|
||||
let mut buffer = [0; 1];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
isize: AddressSize::_8Bit,
|
||||
adwidth: OspiWidth::NONE,
|
||||
adsize: AddressSize::_24bit,
|
||||
dwidth: OspiWidth::SING,
|
||||
instruction: Some(cmd as u32),
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
self.ospi.blocking_read(&mut buffer, transaction).unwrap();
|
||||
// info!("Read w25q64 register: 0x{:x}", buffer[0]);
|
||||
buffer[0]
|
||||
}
|
||||
|
||||
fn write_register(&mut self, cmd: u8, value: u8) {
|
||||
let buffer = [value; 1];
|
||||
let transaction: TransferConfig = TransferConfig {
|
||||
iwidth: OspiWidth::SING,
|
||||
isize: AddressSize::_8Bit,
|
||||
instruction: Some(cmd as u32),
|
||||
adsize: AddressSize::_24bit,
|
||||
adwidth: OspiWidth::NONE,
|
||||
dwidth: OspiWidth::SING,
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
..Default::default()
|
||||
};
|
||||
self.ospi.blocking_write(&buffer, transaction).unwrap();
|
||||
}
|
||||
|
||||
pub fn read_sr(&mut self) -> u8 {
|
||||
self.read_register(CMD_READ_SR)
|
||||
}
|
||||
|
||||
pub fn read_cr(&mut self) -> u8 {
|
||||
self.read_register(CMD_READ_CR)
|
||||
}
|
||||
|
||||
pub fn write_sr(&mut self, value: u8) {
|
||||
self.write_register(CMD_WRITE_SR, value);
|
||||
}
|
||||
|
||||
pub fn write_cr(&mut self, value: u8) {
|
||||
self.write_register(CMD_WRITE_CR, value);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user