..
back
Add new_regular
and new_allocator
to ModuleCodegen
2025-02-23 21:23:38 +08:00
intrinsic
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
abi.rs
Remove an unused lifetime param
2025-02-24 15:11:29 +00:00
allocator.rs
Merge commit '59a81c2ca1edc88ad3ac4b27a8e03977ffb8e73a' into subtree-update_cg_gcc_2025_01_12
2025-01-13 10:53:58 -05:00
asm.rs
codegen #[naked]
functions using global_asm!
2024-12-10 21:41:03 +01:00
attributes.rs
mir_transform: implement forced inlining
2025-01-10 18:37:54 +00:00
base.rs
Add new_regular
and new_allocator
to ModuleCodegen
2025-02-23 21:23:38 +08:00
builder.rs
Rework OperandRef::extract_field
to stop calling to_immediate_scalar
on things which are already immediates
2025-02-19 12:03:40 -08:00
callee.rs
Merge commit '59a81c2ca1edc88ad3ac4b27a8e03977ffb8e73a' into subtree-update_cg_gcc_2025_01_12
2025-01-13 10:53:58 -05:00
common.rs
Rollup merge of #137549 - oli-obk:llvm-ffi, r=davidtwco
2025-03-07 19:15:34 +01:00
consts.rs
Remove an unnecessary lifetime
2025-02-24 15:05:56 +00:00
context.rs
cg_gcc: Directly use rustc_abi instead of reexports
2025-02-04 22:31:56 -08:00
coverageinfo.rs
Unbox and unwrap the contents of StatementKind::Coverage
2024-03-23 22:05:11 +11:00
debuginfo.rs
Auto merge of #136471 - safinaskar:parallel, r=SparrowLii
2025-02-06 10:50:05 +00:00
declare.rs
cg_gcc: Directly use rustc_abi instead of reexports
2025-02-04 22:31:56 -08:00
errors.rs
Merge commit '59a81c2ca1edc88ad3ac4b27a8e03977ffb8e73a' into subtree-update_cg_gcc_2025_01_12
2025-01-13 10:53:58 -05:00
gcc_util.rs
ABI-required target features: warn when they are missing in base CPU (rather than silently enabling them)
2025-01-28 04:40:42 +01:00
int.rs
cg_gcc: stop caring about compiling for unknown targets
2025-02-10 11:19:02 -08:00
lib.rs
Rollup merge of #137741 - cuviper:const_str-raw_entry, r=Mark-Simulacrum
2025-03-03 10:41:00 +01:00
mono_item.rs
Remove Linkage::Private
2025-02-07 16:02:19 +00:00
type_.rs
Generalize BaseTypeCodegenMethods
2025-02-24 15:11:29 +00:00
type_of.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00