nordic-dev.net/rust
nordic-dev.net/rust
2
0
Fork 0
mirror of https://github.com/rust-lang/rust.git synced 2025-04-13 04:26:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

rename BackendRepr::Vector → SimdVector

Browse Source
This commit is contained in:
Ralf Jung 2025-02-28 16:29:07 +01:00
parent 2f581937e1
commit aac65f562b
32 changed files with 92 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/rustc_abi/src/callconv.rs
View File

@ -74,7 +74,7 @@ impl<'a, Ty> TyAndLayout<'a, Ty> {
Ok(HomogeneousAggregate::Homogeneous(Reg { kind, size: self.size }))
}
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
assert!(!self.is_zst());
Ok(HomogeneousAggregate::Homogeneous(Reg {
kind: RegKind::Vector,

12
compiler/rustc_abi/src/layout.rs
View File

@ -386,13 +386,15 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
BackendRepr::Memory { sized: true }
}
// Vectors require at least element alignment, else disable the opt
BackendRepr::Vector { element, count: _ } if element.align(dl).abi > align.abi => {
BackendRepr::SimdVector { element, count: _ }
if element.align(dl).abi > align.abi =>
{
BackendRepr::Memory { sized: true }
}
// the alignment tests passed and we can use this
BackendRepr::Scalar(..)
| BackendRepr::ScalarPair(..)
| BackendRepr::Vector { .. }
| BackendRepr::SimdVector { .. }
| BackendRepr::Memory { .. } => repr,
},
};
@ -464,7 +466,7 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
hide_niches(a);
hide_niches(b);
}
BackendRepr::Vector { element, count: _ } => hide_niches(element),
BackendRepr::SimdVector { element, count: _ } => hide_niches(element),
BackendRepr::Memory { sized: _ } => {}
}
st.largest_niche = None;
@ -1314,7 +1316,9 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
match field.backend_repr {
// For plain scalars, or vectors of them, we can't unpack
// newtypes for `#[repr(C)]`, as that affects C ABIs.
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } if optimize_abi => {
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. }
if optimize_abi =>
{
abi = field.backend_repr;
}
// But scalar pairs are Rust-specific and get

2
compiler/rustc_abi/src/layout/ty.rs
View File

@ -219,7 +219,7 @@ impl<'a, Ty> TyAndLayout<'a, Ty> {
C: HasDataLayout,
{
match self.backend_repr {
BackendRepr::Vector { .. } => self.size == expected_size,
BackendRepr::SimdVector { .. } => self.size == expected_size,
BackendRepr::Memory { .. } => {
if self.fields.count() == 1 && self.fields.offset(0).bytes() == 0 {
self.field(cx, 0).is_single_vector_element(cx, expected_size)

28
compiler/rustc_abi/src/lib.rs
View File

@ -1410,7 +1410,7 @@ impl AddressSpace {
pub enum BackendRepr {
Scalar(Scalar),
ScalarPair(Scalar, Scalar),
Vector {
SimdVector {
element: Scalar,
count: u64,
},
@ -1426,9 +1426,9 @@ impl BackendRepr {
#[inline]
pub fn is_unsized(&self) -> bool {
match *self {
BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) | BackendRepr::Vector { .. } => {
false
}
BackendRepr::Scalar(_)
| BackendRepr::ScalarPair(..)
| BackendRepr::SimdVector { .. } => false,
BackendRepr::Memory { sized } => !sized,
}
}
@ -1467,7 +1467,7 @@ impl BackendRepr {
BackendRepr::Scalar(s) => Some(s.align(cx).abi),
BackendRepr::ScalarPair(s1, s2) => Some(s1.align(cx).max(s2.align(cx)).abi),
// The align of a Vector can vary in surprising ways
BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => None,
BackendRepr::SimdVector { .. } | BackendRepr::Memory { .. } => None,
}
}
@ -1489,7 +1489,7 @@ impl BackendRepr {
Some(size)
}
// The size of a Vector can vary in surprising ways
BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => None,
BackendRepr::SimdVector { .. } | BackendRepr::Memory { .. } => None,
}
}
@ -1500,8 +1500,8 @@ impl BackendRepr {
BackendRepr::ScalarPair(s1, s2) => {
BackendRepr::ScalarPair(s1.to_union(), s2.to_union())
}
BackendRepr::Vector { element, count } => {
BackendRepr::Vector { element: element.to_union(), count }
BackendRepr::SimdVector { element, count } => {
BackendRepr::SimdVector { element: element.to_union(), count }
}
BackendRepr::Memory { .. } => BackendRepr::Memory { sized: true },
}
@ -1513,8 +1513,8 @@ impl BackendRepr {
// We do *not* ignore the sign since it matters for some ABIs (e.g. s390x).
(BackendRepr::Scalar(l), BackendRepr::Scalar(r)) => l.primitive() == r.primitive(),
(
BackendRepr::Vector { element: element_l, count: count_l },
BackendRepr::Vector { element: element_r, count: count_r },
BackendRepr::SimdVector { element: element_l, count: count_l },
BackendRepr::SimdVector { element: element_r, count: count_r },
) => element_l.primitive() == element_r.primitive() && count_l == count_r,
(BackendRepr::ScalarPair(l1, l2), BackendRepr::ScalarPair(r1, r2)) => {
l1.primitive() == r1.primitive() && l2.primitive() == r2.primitive()
@ -1735,7 +1735,7 @@ impl<FieldIdx: Idx, VariantIdx: Idx> LayoutData<FieldIdx, VariantIdx> {
/// Returns `true` if this is an aggregate type (including a ScalarPair!)
pub fn is_aggregate(&self) -> bool {
match self.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => false,
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => false,
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => true,
}
}
@ -1877,9 +1877,9 @@ impl<FieldIdx: Idx, VariantIdx: Idx> LayoutData<FieldIdx, VariantIdx> {
/// non-trivial alignment constraints. You probably want to use `is_1zst` instead.
pub fn is_zst(&self) -> bool {
match self.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) | BackendRepr::Vector { .. } => {
false
}
BackendRepr::Scalar(_)
| BackendRepr::ScalarPair(..)
| BackendRepr::SimdVector { .. } => false,
BackendRepr::Memory { sized } => sized && self.size.bytes() == 0,
}
}

4
compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs
View File

@ -84,7 +84,7 @@ impl<'tcx> ArgAbiExt<'tcx> for ArgAbi<'tcx, Ty<'tcx>> {
AbiParam::new(scalar_to_clif_type(tcx, scalar)),
attrs
)],
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
let vector_ty = crate::intrinsics::clif_vector_type(tcx, self.layout);
smallvec![AbiParam::new(vector_ty)]
}
@ -135,7 +135,7 @@ impl<'tcx> ArgAbiExt<'tcx> for ArgAbi<'tcx, Ty<'tcx>> {
BackendRepr::Scalar(scalar) => {
(None, vec![AbiParam::new(scalar_to_clif_type(tcx, scalar))])
}
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
let vector_ty = crate::intrinsics::clif_vector_type(tcx, self.layout);
(None, vec![AbiParam::new(vector_ty)])
}

2
compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
View File

@ -53,7 +53,7 @@ fn report_atomic_type_validation_error<'tcx>(
pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx>) -> Type {
let (element, count) = match layout.backend_repr {
BackendRepr::Vector { element, count } => (element, count),
BackendRepr::SimdVector { element, count } => (element, count),
_ => unreachable!(),
};

8
compiler/rustc_codegen_cranelift/src/value_and_place.rs
View File

@ -173,9 +173,11 @@ impl<'tcx> CValue<'tcx> {
CValueInner::ByRef(ptr, None) => {
let clif_ty = match layout.backend_repr {
BackendRepr::Scalar(scalar) => scalar_to_clif_type(fx.tcx, scalar),
BackendRepr::Vector { element, count } => scalar_to_clif_type(fx.tcx, element)
.by(u32::try_from(count).unwrap())
.unwrap(),
BackendRepr::SimdVector { element, count } => {
scalar_to_clif_type(fx.tcx, element)
.by(u32::try_from(count).unwrap())
.unwrap()
}
_ => unreachable!("{:?}", layout.ty),
};
let mut flags = MemFlags::new();

2
compiler/rustc_codegen_gcc/src/intrinsic/mod.rs
View File

@ -312,7 +312,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc
let layout = self.layout_of(tp_ty).layout;
let _use_integer_compare = match layout.backend_repr() {
Scalar(_) | ScalarPair(_, _) => true,
Vector { .. } => false,
SimdVector { .. } => false,
Memory { .. } => {
// For rusty ABIs, small aggregates are actually passed
// as `RegKind::Integer` (see `FnAbi::adjust_for_abi`),

10
compiler/rustc_codegen_gcc/src/type_of.rs
View File

@ -63,7 +63,7 @@ fn uncached_gcc_type<'gcc, 'tcx>(
) -> Type<'gcc> {
match layout.backend_repr {
BackendRepr::Scalar(_) => bug!("handled elsewhere"),
BackendRepr::Vector { ref element, count } => {
BackendRepr::SimdVector { ref element, count } => {
let element = layout.scalar_gcc_type_at(cx, element, Size::ZERO);
let element =
// NOTE: gcc doesn't allow pointer types in vectors.
@ -178,7 +178,7 @@ pub trait LayoutGccExt<'tcx> {
impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> {
fn is_gcc_immediate(&self) -> bool {
match self.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => true,
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => true,
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => false,
}
}
@ -186,9 +186,9 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> {
fn is_gcc_scalar_pair(&self) -> bool {
match self.backend_repr {
BackendRepr::ScalarPair(..) => true,
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => {
false
}
BackendRepr::Scalar(_)
| BackendRepr::SimdVector { .. }
| BackendRepr::Memory { .. } => false,
}
}

39
compiler/rustc_codegen_llvm/src/asm.rs
View File

@ -939,9 +939,10 @@ fn llvm_fixup_input<'ll, 'tcx>(
}
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
}
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
if layout.size.bytes() == 8 =>
{
(
AArch64(AArch64InlineAsmRegClass::vreg_low16),
BackendRepr::SimdVector { element, count },
) if layout.size.bytes() == 8 => {
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
let vec_ty = bx.cx.type_vector(elem_ty, count);
let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
@ -954,7 +955,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
}
(
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
BackendRepr::Vector { .. },
BackendRepr::SimdVector { .. },
) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
(
X86(
@ -989,7 +990,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
| X86InlineAsmRegClass::ymm_reg
| X86InlineAsmRegClass::zmm_reg,
),
BackendRepr::Vector { element, count: count @ (8 | 16) },
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
}
@ -1026,7 +1027,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
BackendRepr::Vector { element, count: count @ (4 | 8) },
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
}
@ -1099,9 +1100,10 @@ fn llvm_fixup_output<'ll, 'tcx>(
}
value
}
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
if layout.size.bytes() == 8 =>
{
(
AArch64(AArch64InlineAsmRegClass::vreg_low16),
BackendRepr::SimdVector { element, count },
) if layout.size.bytes() == 8 => {
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
@ -1114,7 +1116,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
}
(
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
BackendRepr::Vector { .. },
BackendRepr::SimdVector { .. },
) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
(
X86(
@ -1145,7 +1147,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
| X86InlineAsmRegClass::ymm_reg
| X86InlineAsmRegClass::zmm_reg,
),
BackendRepr::Vector { element, count: count @ (8 | 16) },
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
}
@ -1182,7 +1184,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
BackendRepr::Vector { element, count: count @ (4 | 8) },
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
}
@ -1243,9 +1245,10 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
let count = 16 / layout.size.bytes();
cx.type_vector(elem_ty, count)
}
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
if layout.size.bytes() == 8 =>
{
(
AArch64(AArch64InlineAsmRegClass::vreg_low16),
BackendRepr::SimdVector { element, count },
) if layout.size.bytes() == 8 => {
let elem_ty = llvm_asm_scalar_type(cx, element);
cx.type_vector(elem_ty, count * 2)
}
@ -1256,7 +1259,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
}
(
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
BackendRepr::Vector { .. },
BackendRepr::SimdVector { .. },
) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
(
X86(
@ -1284,7 +1287,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
| X86InlineAsmRegClass::ymm_reg
| X86InlineAsmRegClass::zmm_reg,
),
BackendRepr::Vector { element, count: count @ (8 | 16) },
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
) if element.primitive() == Primitive::Float(Float::F16) => {
cx.type_vector(cx.type_i16(), count)
}
@ -1321,7 +1324,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
BackendRepr::Vector { element, count: count @ (4 | 8) },
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
cx.type_vector(cx.type_i16(), count)
}

2
compiler/rustc_codegen_llvm/src/intrinsic.rs
View File

@ -470,7 +470,7 @@ impl<'ll, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
let layout = self.layout_of(tp_ty).layout;
let use_integer_compare = match layout.backend_repr() {
Scalar(_) | ScalarPair(_, _) => true,
Vector { .. } => false,
SimdVector { .. } => false,
Memory { .. } => {
// For rusty ABIs, small aggregates are actually passed
// as `RegKind::Integer` (see `FnAbi::adjust_for_abi`),

10
compiler/rustc_codegen_llvm/src/type_of.rs
View File

@ -19,7 +19,7 @@ fn uncached_llvm_type<'a, 'tcx>(
) -> &'a Type {
match layout.backend_repr {
BackendRepr::Scalar(_) => bug!("handled elsewhere"),
BackendRepr::Vector { element, count } => {
BackendRepr::SimdVector { element, count } => {
let element = layout.scalar_llvm_type_at(cx, element);
return cx.type_vector(element, count);
}
@ -171,7 +171,7 @@ pub(crate) trait LayoutLlvmExt<'tcx> {
impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
fn is_llvm_immediate(&self) -> bool {
match self.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => true,
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => true,
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => false,
}
}
@ -179,9 +179,9 @@ impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
fn is_llvm_scalar_pair(&self) -> bool {
match self.backend_repr {
BackendRepr::ScalarPair(..) => true,
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => {
false
}
BackendRepr::Scalar(_)
| BackendRepr::SimdVector { .. }
| BackendRepr::Memory { .. } => false,
}
}

2
compiler/rustc_codegen_ssa/src/mir/naked_asm.rs
View File

@ -349,7 +349,7 @@ fn wasm_type<'tcx>(
PassMode::Direct(_) => {
let direct_type = match arg_abi.layout.backend_repr {
BackendRepr::Scalar(scalar) => wasm_primitive(scalar.primitive(), ptr_type),
BackendRepr::Vector { .. } => "v128",
BackendRepr::SimdVector { .. } => "v128",
BackendRepr::Memory { .. } => {
// FIXME: remove this branch once the wasm32-unknown-unknown ABI is fixed
let _ = WasmCAbi::Legacy;

6
compiler/rustc_codegen_ssa/src/mir/operand.rs
View File

@ -359,7 +359,7 @@ impl<'a, 'tcx, V: CodegenObject> OperandRef<'tcx, V> {
let offset = self.layout.fields.offset(i);
if !bx.is_backend_ref(self.layout) && bx.is_backend_ref(field) {
if let BackendRepr::Vector { count, .. } = self.layout.backend_repr
if let BackendRepr::SimdVector { count, .. } = self.layout.backend_repr
&& let BackendRepr::Memory { sized: true } = field.backend_repr
&& count.is_power_of_two()
{
@ -404,7 +404,7 @@ impl<'a, 'tcx, V: CodegenObject> OperandRef<'tcx, V> {
}
};
OperandValue::Immediate(match field.backend_repr {
BackendRepr::Vector { .. } => imm,
BackendRepr::SimdVector { .. } => imm,
BackendRepr::Scalar(out_scalar) => {
let Some(in_scalar) = in_scalar else {
span_bug!(
@ -666,7 +666,7 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
// However, some SIMD types do not actually use the vector ABI
// (in particular, packed SIMD types do not). Ensure we exclude those.
let layout = bx.layout_of(constant_ty);
if let BackendRepr::Vector { .. } = layout.backend_repr {
if let BackendRepr::SimdVector { .. } = layout.backend_repr {
let (llval, ty) = self.immediate_const_vector(bx, constant);
return OperandRef {
val: OperandValue::Immediate(llval),

2
compiler/rustc_codegen_ssa/src/mir/rvalue.rs
View File

@ -1190,7 +1190,7 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
assert!(!self.cx.is_backend_scalar_pair(layout));
OperandValueKind::Immediate(match layout.backend_repr {
abi::BackendRepr::Scalar(s) => s,
abi::BackendRepr::Vector { element, .. } => element,
abi::BackendRepr::SimdVector { element, .. } => element,
x => span_bug!(self.mir.span, "Couldn't translate {x:?} as backend immediate"),
})
} else if self.cx.is_backend_scalar_pair(layout) {

2
compiler/rustc_const_eval/src/interpret/validity.rs
View File

@ -1296,7 +1296,7 @@ impl<'rt, 'tcx, M: Machine<'tcx>> ValueVisitor<'tcx, M> for ValidityVisitor<'rt,
self.visit_scalar(b, b_layout)?;
}
}
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
// No checks here, we assume layout computation gets this right.
// (This is harder to check since Miri does not represent these as `Immediate`. We
// also cannot use field projections since this might be a newtype around a vector.)

2
compiler/rustc_const_eval/src/util/check_validity_requirement.rs
View File

@ -117,7 +117,7 @@ fn check_validity_requirement_lax<'tcx>(
BackendRepr::ScalarPair(s1, s2) => {
scalar_allows_raw_init(s1) && scalar_allows_raw_init(s2)
}
BackendRepr::Vector { element: s, count } => count == 0 || scalar_allows_raw_init(s),
BackendRepr::SimdVector { element: s, count } => count == 0 || scalar_allows_raw_init(s),
BackendRepr::Memory { .. } => true, // Fields are checked below.
};
if !valid {

2
compiler/rustc_mir_transform/src/gvn.rs
View File

@ -1567,7 +1567,7 @@ impl<'body, 'tcx> VnState<'body, 'tcx> {
BackendRepr::ScalarPair(a, b) => {
!a.is_always_valid(&self.ecx) || !b.is_always_valid(&self.ecx)
}
BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => false,
BackendRepr::SimdVector { .. } | BackendRepr::Memory { .. } => false,
}
}

2
compiler/rustc_monomorphize/src/mono_checks/abi_check.rs
View File

@ -18,7 +18,7 @@ fn uses_vector_registers(mode: &PassMode, repr: &BackendRepr) -> bool {
cast.prefix.iter().any(|r| r.is_some_and(|x| x.kind == RegKind::Vector))
|| cast.rest.unit.kind == RegKind::Vector
}
PassMode::Direct(..) | PassMode::Pair(..) => matches!(repr, BackendRepr::Vector { .. }),
PassMode::Direct(..) | PassMode::Pair(..) => matches!(repr, BackendRepr::SimdVector { .. }),
}
}

2
compiler/rustc_smir/src/rustc_smir/convert/abi.rs
View File

@ -206,7 +206,7 @@ impl<'tcx> Stable<'tcx> for rustc_abi::BackendRepr {
rustc_abi::BackendRepr::ScalarPair(first, second) => {
ValueAbi::ScalarPair(first.stable(tables), second.stable(tables))
}
rustc_abi::BackendRepr::Vector { element, count } => {
rustc_abi::BackendRepr::SimdVector { element, count } => {
ValueAbi::Vector { element: element.stable(tables), count }
}
rustc_abi::BackendRepr::Memory { sized } => ValueAbi::Aggregate { sized },

4
compiler/rustc_target/src/callconv/loongarch.rs
View File

@ -25,7 +25,7 @@ struct CannotUseFpConv;
fn is_loongarch_aggregate<Ty>(arg: &ArgAbi<'_, Ty>) -> bool {
match arg.layout.backend_repr {
BackendRepr::Vector { .. } => true,
BackendRepr::SimdVector { .. } => true,
_ => arg.layout.is_aggregate(),
}
}
@ -80,7 +80,7 @@ where
}
}
},
BackendRepr::Vector { .. } => return Err(CannotUseFpConv),
BackendRepr::SimdVector { .. } => return Err(CannotUseFpConv),
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => match arg_layout.fields {
FieldsShape::Primitive => {
unreachable!("aggregates can't have `FieldsShape::Primitive`")

6
compiler/rustc_target/src/callconv/mod.rs
View File

@ -357,7 +357,7 @@ impl<'a, Ty> ArgAbi<'a, Ty> {
scalar_attrs(&layout, a, Size::ZERO),
scalar_attrs(&layout, b, a.size(cx).align_to(b.align(cx).abi)),
),
BackendRepr::Vector { .. } => PassMode::Direct(ArgAttributes::new()),
BackendRepr::SimdVector { .. } => PassMode::Direct(ArgAttributes::new()),
BackendRepr::Memory { .. } => Self::indirect_pass_mode(&layout),
};
ArgAbi { layout, mode }
@ -759,7 +759,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
if arg_idx.is_none()
&& arg.layout.size > Primitive::Pointer(AddressSpace::DATA).size(cx) * 2
&& !matches!(arg.layout.backend_repr, BackendRepr::Vector { .. })
&& !matches!(arg.layout.backend_repr, BackendRepr::SimdVector { .. })
{
// Return values larger than 2 registers using a return area
// pointer. LLVM and Cranelift disagree about how to return
@ -826,7 +826,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
}
}
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
// This is a fun case! The gist of what this is doing is
// that we want callers and callees to always agree on the
// ABI of how they pass SIMD arguments. If we were to *not*

4
compiler/rustc_target/src/callconv/riscv.rs
View File

@ -31,7 +31,7 @@ struct CannotUseFpConv;
fn is_riscv_aggregate<Ty>(arg: &ArgAbi<'_, Ty>) -> bool {
match arg.layout.backend_repr {
BackendRepr::Vector { .. } => true,
BackendRepr::SimdVector { .. } => true,
_ => arg.layout.is_aggregate(),
}
}
@ -86,7 +86,7 @@ where
}
}
},
BackendRepr::Vector { .. } => return Err(CannotUseFpConv),
BackendRepr::SimdVector { .. } => return Err(CannotUseFpConv),
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => match arg_layout.fields {
FieldsShape::Primitive => {
unreachable!("aggregates can't have `FieldsShape::Primitive`")

4
compiler/rustc_target/src/callconv/s390x.rs
View File

@ -8,7 +8,7 @@ use crate::spec::HasTargetSpec;
fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) {
let size = ret.layout.size;
if size.bits() <= 128 && matches!(ret.layout.backend_repr, BackendRepr::Vector { .. }) {
if size.bits() <= 128 && matches!(ret.layout.backend_repr, BackendRepr::SimdVector { .. }) {
return;
}
if !ret.layout.is_aggregate() && size.bits() <= 64 {
@ -40,7 +40,7 @@ where
let size = arg.layout.size;
if size.bits() <= 128 {
if let BackendRepr::Vector { .. } = arg.layout.backend_repr {
if let BackendRepr::SimdVector { .. } = arg.layout.backend_repr {
// pass non-wrapped vector types using `PassMode::Direct`
return;
}

2
compiler/rustc_target/src/callconv/x86.rs
View File

@ -109,7 +109,7 @@ where
{
match layout.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) => false,
BackendRepr::Vector { .. } => true,
BackendRepr::SimdVector { .. } => true,
BackendRepr::Memory { .. } => {
for i in 0..layout.fields.count() {
if contains_vector(cx, layout.field(cx, i)) {

2
compiler/rustc_target/src/callconv/x86_64.rs
View File

@ -56,7 +56,7 @@ where
Primitive::Float(_) => Class::Sse,
},
BackendRepr::Vector { .. } => Class::Sse,
BackendRepr::SimdVector { .. } => Class::Sse,
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => {
for i in 0..layout.fields.count() {

2
compiler/rustc_target/src/callconv/x86_win64.rs
View File

@ -18,7 +18,7 @@ pub(crate) fn compute_abi_info<Ty>(cx: &impl HasTargetSpec, fn_abi: &mut FnAbi<'
_ => a.make_indirect(),
}
}
BackendRepr::Vector { .. } => {
BackendRepr::SimdVector { .. } => {
// FIXME(eddyb) there should be a size cap here
// (probably what clang calls "illegal vectors").
}

2
compiler/rustc_target/src/callconv/xtensa.rs
View File

@ -116,7 +116,7 @@ where
fn is_xtensa_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool {
match arg.layout.backend_repr {
BackendRepr::Vector { .. } => true,
BackendRepr::SimdVector { .. } => true,
_ => arg.layout.is_aggregate(),
}
}

2
compiler/rustc_ty_utils/src/abi.rs
View File

@ -460,7 +460,7 @@ fn fn_abi_sanity_check<'tcx>(
// `layout.backend_repr` and ignore everything else. We should just reject
//`Aggregate` entirely here, but some targets need to be fixed first.
match arg.layout.backend_repr {
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => {}
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => {}
BackendRepr::ScalarPair(..) => {
panic!("`PassMode::Direct` used for ScalarPair type {}", arg.layout.ty)
}

2
compiler/rustc_ty_utils/src/layout.rs
View File

@ -553,7 +553,7 @@ fn layout_of_uncached<'tcx>(
)
} else {
(
BackendRepr::Vector { element: e_abi, count: e_len },
BackendRepr::SimdVector { element: e_abi, count: e_len },
dl.llvmlike_vector_align(size),
)
};

2
compiler/rustc_ty_utils/src/layout/invariant.rs
View File

@ -234,7 +234,7 @@ pub(super) fn layout_sanity_check<'tcx>(cx: &LayoutCx<'tcx>, layout: &TyAndLayou
"`ScalarPair` second field with bad ABI in {inner:#?}",
);
}
BackendRepr::Vector { element, count } => {
BackendRepr::SimdVector { element, count } => {
let align = layout.align.abi;
let size = layout.size;
let element_align = element.align(cx).abi;

2
src/tools/rust-analyzer/crates/hir-ty/src/layout.rs
View File

@ -192,7 +192,7 @@ fn layout_of_simd_ty(
Ok(Arc::new(Layout {
variants: Variants::Single { index: struct_variant_idx() },
fields,
backend_repr: BackendRepr::Vector { element: e_abi, count: e_len },
backend_repr: BackendRepr::SimdVector { element: e_abi, count: e_len },
largest_niche: e_ly.largest_niche,
uninhabited: false,
size,