Commit Graph

63 Commits

Author SHA1 Message Date
Ian Douglas Scott
2ac8dee44f Add inline assembly support for m68k 2023-04-12 17:58:15 -07:00
klensy
076116bb4c replace LLVMRustAppendModuleInlineAsm with LLVMAppendModuleInlineAsm, LLVMRustMetadataTypeInContext with LLVMMetadataTypeInContext 2023-04-04 15:12:35 +03:00
Erik Desjardins
009192b01b abi: add AddressSpace field to Primitive::Pointer
...and remove it from `PointeeInfo`, which isn't meant for this.

There are still various places (marked with FIXMEs) that assume all pointers
have the same size and alignment. Fixing this requires parsing non-default
address spaces in the data layout string, which will be done in a followup.
2023-01-22 23:41:39 -05:00
Maybe Waffle
6a28fb42a8 Remove double spaces after dots in comments 2023-01-17 08:09:33 +00:00
Matthias Krüger
3af7df91fc use &str / String literals instead of format!() 2022-12-18 16:17:46 +01:00
Matthias Krüger
f6ca5aa19a
Rollup merge of #103977 - TimNN:memory-effects, r=nikic
LLVM 16: Switch to using MemoryEffects

This adapts the compiler to the changes required by 304f1d59ca.

AFAICT, `WriteOnly` isn't used by the compiler, all `ReadNone` uses were migrated and the remaining use of `ReadOnly` is only for function parameters.

To simplify the FFI, this PR uses an enum to represent `MemoryEffects` across the FFI boundary, which then gets mapped to the matching static factory method when constructing the attribute.

Fixes #103961.

`@rustbot` label +llvm-main

r? `@nikic`
2022-11-05 00:02:05 +01:00
Tim Neumann
c15cfc91c4 LLVM 16: Switch to using MemoryEffects 2022-11-04 17:58:16 +00:00
Matthias Krüger
2aa8ad6d39
Rollup merge of #103897 - Amanieu:llvm-58384, r=davidtwco
asm: Work around LLVM bug on AArch64

Upstream issue: https://github.com/llvm/llvm-project/issues/58384

LLVM gets confused if we assign a 32-bit value to a 64-bit register, so pass the 32-bit register name to LLVM in that case.
2022-11-04 18:52:27 +01:00
bors
47c008e440 Auto merge of #103098 - Amanieu:asm-tied-fixed, r=bjorn3
asm: Match clang behavior for inlateout fixed register operands

We have 2 options for representing LLVM constraints for `inlateout` operands on a fixed register (e.g. `r0`): `={r0},0` or `={r0},{r0}`.

This PR changes the behavior to the latter, which matches the behavior of Clang since https://reviews.llvm.org/D87279.
2022-11-04 10:39:04 +00:00
Amanieu d'Antras
03e4c76dcf asm: Work around LLVM bug on AArch64
Upstream issue: https://github.com/llvm/llvm-project/issues/58384

LLVM gets confused if we assign a 32-bit value to a 64-bit register, so
pass the 32-bit register name to LLVM in that case.
2022-11-02 19:52:49 +00:00
Amanieu d'Antras
6bfe7f01dc asm: Match clang behavior for inlateout fixed register operands
We have 2 options for representing LLVM constraints for `inlateout`
operands on a fixed register (e.g. `r0`): `={r0},0` or `={r0},{r0}`.

This PR changes the behavior to the latter, which matches the behavior
of Clang since https://reviews.llvm.org/D87279.
2022-10-15 23:42:11 +01:00
Guillaume Gomez
2214748ade Add links to relevant pages to find constraint information 2022-10-13 22:05:49 +02:00
bjorn3
62cf644c64 Merge apply_attrs_callsite into call and invoke
Some codegen backends are not able to apply callsite attrs after the fact.
2022-10-01 17:01:31 +00:00
Oli Scherer
ee3c835018 Always import all tracing macros for the entire crate instead of piecemeal by module 2022-09-01 14:54:27 +00:00
Josh Stone
2970ad8aee Update the minimum external LLVM to 13 2022-08-14 13:46:51 -07:00
Connor Horman
658be0d1cf Add tmm_reg clobbers 2022-05-16 20:15:06 -04:00
Dylan DPC
69e45d73b9
Rollup merge of #95740 - Amanieu:kreg0, r=nagisa
asm: Add a kreg0 register class on x86 which includes k0

Previously we only exposed a kreg register class which excludes the k0
register since it can't be used in many instructions. However k0 is a
valid register and we need to have a way of marking it as clobbered for
clobber_abi.

Fixes #94977
2022-04-19 22:57:39 +02:00
Amanieu d'Antras
b2bc46938c asm: Add a kreg0 register class on x86 which includes k0
Previously we only exposed a kreg register class which excludes the k0
register since it can't be used in many instructions. However k0 is a
valid register and we need to have a way of marking it as clobbered for
clobber_abi.

Fixes #94977
2022-04-19 17:14:23 +02:00
Amanieu d'Antras
547405e801 Add codegen for global_asm! sym operands 2022-04-15 14:36:30 +01:00
Luqman Aden
bf3ef0da0c Switch to the 'normal' basic block for writing asm outputs if needed.
We may sometimes emit an `invoke` instead of a `call` for inline
assembly during the MIR -> LLVM IR lowering. But we failed to update
the IR builder's current basic block before writing the results to the
outputs. This would result in invalid IR because the basic block would
end in a `store` instruction, which isn't a valid terminator.
2022-04-09 15:25:46 -04:00
Oli Scherer
d32ce37a17 Mark scalar layout unions so that backends that do not support partially initialized scalars can special case them. 2022-04-05 13:18:21 +00:00
Erik Desjardins
30d3ce0674 Add LLVM attributes in batches instead of individually
This should improve performance.
2022-02-26 13:14:55 -05:00
William D. Jones
19809ed76d Add preliminary support for inline assembly for msp430. 2022-01-22 23:42:46 -05:00
bjorn3
991cbd1503 Use Symbol for target features in asm handling
This saves a couple of Symbol::intern calls
2022-01-17 18:06:27 +01:00
Tomasz Miąsko
000b36c505 Remove deprecated LLVM-style inline assembly 2022-01-12 18:51:31 +01:00
LegionMammal978
4937a55dfb Remove in_band_lifetimes from rustc_codegen_llvm
See #91867 for more information.
2021-12-16 14:43:32 -05:00
Matthias Krüger
40988591ec
Rollup merge of #91625 - est31:remove_indexes, r=oli-obk
Remove redundant [..]s
2021-12-10 22:40:36 +01:00
est31
15de4cbc4b Remove redundant [..]s 2021-12-09 00:01:29 +01:00
Amanieu d'Antras
908f300dd7 Remove the reg_thumb register class for asm! on ARM
Also restricts r8-r14 from being used on Thumb1 targets as per #90736.
2021-12-07 23:54:09 +00:00
Andrew Dona-Couch
c6e8ae1a6c Implement inline asm! for AVR platform 2021-12-06 01:02:49 -05:00
cynecx
91021de1f6 LLVM codgen support for unwinding inline assembly 2021-12-03 23:51:49 +01:00
cynecx
491dd1f387 Adjust llvm wrapper for unwinding support for inlineasm 2021-12-03 23:51:49 +01:00
Alex Crichton
d2a3c24a95 Update more rustc/libtest things for wasm64
* Add wasm64 variants for inline assembly along the same lines as wasm32
* Update a few directives in libtest to check for `target_family`
  instead of `target_arch`
* Update some rustc codegen and typechecks specialized for wasm32 to
  also work for wasm64.
2021-11-10 08:35:42 -08:00
Yuki Okushi
12647eab79
Properly check target_features not to trigger an assertion 2021-10-26 11:02:51 +09:00
Guillaume Gomez
759eba0a08 Fix clippy lints 2021-10-01 23:17:19 +02:00
Andreas Liljeqvist
5b2f757dae Make abi::Abi Copy and remove a *lot* of refs
fix

fix

Remove more refs and clones

fix

more

fix
2021-09-09 10:41:19 +02:00
Mara Bos
494c563f3b
Rollup merge of #88350 - programmerjake:add-ppc-cr-xer-clobbers, r=Amanieu
add support for clobbering xer, cr, and cr[0-7] for asm! on OpenPower/PowerPC

Fixes #88315
2021-09-01 09:23:26 +02:00
Jacob Lifshay
5802f60355 add support for clobbering xer, cr, and cr[0-7] for asm! on OpenPower/PowerPC
Fixes #88315
2021-08-25 22:08:27 -07:00
linux1
5f5afba5fb Feat: added s390x reg-definitions, constraint codes, and tests 2021-08-22 17:55:03 -04:00
linux1
f28793dd13 Feat: added inline asm support for s390x 2021-08-22 17:55:03 -04:00
bors
85109e257a Auto merge of #87581 - Amanieu:asm_clobber_abi, r=nagisa
Add support for clobber_abi to asm!

This PR adds the `clobber_abi` feature that was proposed in #81092.

Fixes #81092

cc `@rust-lang/wg-inline-asm`

r? `@nagisa`
2021-08-14 22:29:27 +00:00
Gary Guo
1fb1643129 Implement black_box using intrinsic
The new implementation allows some `memcpy`s to be optimized away,
so the uninit value in ui/sanitize/memory.rs is constructed directly
onto the return place. Therefore the sanitizer now says that the
value is allocated by `main` rather than `random`.
2021-08-12 16:16:57 +01:00
Amanieu d'Antras
2f4612260d Mark RISC-V vector state as clobbered in inline assembly 2021-08-12 12:42:58 +01:00
Josh Stone
183d79cc09 Prepare call/invoke for opaque pointers
Rather than relying on `getPointerElementType()` from LLVM function
pointers, we now pass the function type explicitly when building `call`
or `invoke` instructions.
2021-08-05 10:58:55 -07:00
bors
99f8efec46 Auto merge of #86416 - Amanieu:asm_clobber_only, r=nagisa
Add clobber-only register classes for asm!

These are needed to properly express a function call ABI using a clobber
list, even though we don't support passing actual values into/out of
these registers.
2021-07-11 01:06:58 +00:00
Amanieu d'Antras
e1c3f5e017 Add clobber-only register classes for asm!
These are needed to properly express a function call ABI using a clobber
list, even though we don't support passing actual values into/out of
these registers.
2021-07-10 17:29:00 +02:00
Alessandro Decina
b2a6967114 Add support for BPF inline assembly 2021-05-23 18:03:27 +10:00
Dr. Chat
69acee3ffe Add asm!() support for PowerPC64 2021-05-13 22:31:47 -05:00
Amanieu d'Antras
5918ee4317 Add support for const operands and options to global_asm!
On x86, the default syntax is also switched to Intel to match asm!
2021-05-13 22:31:57 +01:00
Dr. Chat
b1bb5d662c Add initial asm!() support for PowerPC
This includes GPRs and FPRs only
2021-05-11 19:04:16 -05:00