Commit Graph

1439 Commits

Author SHA1 Message Date
Alex Crichton
f534974037 Add a new wide-arithmetic feature for WebAssembly
This commit adds a new rustc target feature named `wide-arithmetic` for
WebAssembly targets. This corresponds to the [wide-arithmetic] proposal
for WebAssembly which adds new instructions catered towards accelerating
integer arithmetic larger than 64-bits. This proposal to WebAssembly is
not standard yet so this new feature is flagged as an unstable target
feature. Additionally Rust's LLVM version doesn't support this new
feature yet since support will first be added in LLVM 20, so the
feature filtering logic for LLVM is updated to handle this.

I'll also note that I'm not currently planning to add wasm-specific
intrinsics to `std::arch::wasm32` at this time. The currently proposed
instructions are all accessible through `i128` or `u128`-based
operations which Rust already supports, so intrinsic shouldn't be
necessary to get access to these new instructions.

[wide-arithmetic]: https://github.com/WebAssembly/wide-arithmetic
2024-10-28 08:11:47 -07:00
bors
f7cf41c973 Auto merge of #131900 - mrkajetanp:target-feature-pauth-lr, r=Amanieu
rustc_target: Add pauth-lr aarch64 target feature

Add the pauth-lr target feature, corresponding to aarch64 FEAT_PAuth_LR. This feature has been added in LLVM 19.
It is currently not supported by the Linux hwcap and so we cannot add runtime feature detection for it at this time.

r? `@Amanieu`
2024-10-27 00:09:49 +00:00
许杰友 Jieyou Xu (Joe)
656a2ec0bd
Rollup merge of #132174 - RalfJung:pclmulqdq, r=calebzulawski
x86 target features: make pclmulqdq imply sse2

Based on comments in https://github.com/rust-lang/stdarch/issues/1661

Fixes https://github.com/rust-lang/stdarch/issues/1661
2024-10-26 22:01:13 +08:00
Ralf Jung
867640e24d x86 target features: make pclmulqdq imply sse2 2024-10-26 09:48:39 +02:00
Rémy Rakic
bd8477b562 Revert "Emit error when calling/declaring functions with unavailable vectors."
This reverts commit 5af56cac38.
2024-10-25 20:42:09 +00:00
bors
6faf0bd3e5 Auto merge of #127731 - veluca93:abi_checks, r=RalfJung
Emit future-incompatibility lint when calling/declaring functions with vectors that require missing target feature

On some architectures, vector types may have a different ABI depending on whether the relevant target features are enabled. (The ABI when the feature is disabled is often not specified, but LLVM implements some de-facto ABI.)

As discussed in https://github.com/rust-lang/lang-team/issues/235, this turns out to very easily lead to unsound code.

This commit makes it a post-monomorphization error to declare or call functions using those vector types in a context in which the corresponding target features are disabled, if using an ABI for which the difference is relevant. This ensures that these functions are always called with a consistent ABI.

See the [nomination comment](https://github.com/rust-lang/rust/pull/127731#issuecomment-2288558187) for more discussion.

r? RalfJung

Part of https://github.com/rust-lang/rust/issues/116558
2024-10-25 15:17:47 +00:00
WANG Rui
baa3b6d95e Enable LSX feature for LoongArch Linux targets 2024-10-25 21:35:19 +08:00
Luca Versari
5af56cac38 Emit error when calling/declaring functions with unavailable vectors.
On some architectures, vector types may have a different ABI when
relevant target features are enabled.

As discussed in https://github.com/rust-lang/lang-team/issues/235, this
turns out to very easily lead to unsound code.

This commit makes it an error to declare or call functions using those
vector types in a context in which the corresponding target features are
disabled, if using an ABI for which the difference is relevant.
2024-10-25 08:46:40 +02:00
Stuart Cook
40d787234b
Rollup merge of #131169 - madsmtm:target-info-nto-vendor, r=wesleywiser
Fix `target_vendor` in QNX Neutrino targets

The `x86_64-pc-nto-qnx710` and `i586-pc-nto-qnx700` targets have `pc` in their target triple names, but the vendor was set to the default `"unknown"`.

CC target maintainers `@flba-eb,` `@gh-tr,` `@jonathanpallant` and `@japaric`
2024-10-24 14:19:53 +11:00
bors
b8bb2968ce Auto merge of #132079 - fmease:rollup-agrd358, r=fmease
Rollup of 9 pull requests

Successful merges:

 - #130991 (Vectorized SliceContains)
 - #131928 (rustdoc: Document `markdown` module.)
 - #131955 (Set `signext` or `zeroext` for integer arguments on RISC-V and LoongArch64)
 - #131979 (Minor tweaks to `compare_impl_item.rs`)
 - #132036 (Add a test case for #131164)
 - #132039 (Specialize `read_exact` and `read_buf_exact` for `VecDeque`)
 - #132060 ("innermost", "outermost", "leftmost", and "rightmost" don't need hyphens)
 - #132065 (Clarify documentation of `ptr::dangling()` function)
 - #132066 (Fix a typo in documentation of `pointer::sub_ptr()`)

r? `@ghost`
`@rustbot` modify labels: rollup
2024-10-23 22:28:57 +00:00
Graydon Hoare
3ba87498fa
Fix rustc_target test: wasmNN-none should support dynamic linking 2024-10-22 23:04:44 -07:00
Graydon Hoare
212d516ab0
Address review comments on wasm32v1-none target 2024-10-22 23:04:44 -07:00
Graydon Hoare
e14d6d8314
Add wasm32v1-none target (compiler-team/#791) 2024-10-22 23:04:44 -07:00
Asuna
57bffe1d59 Set signext or zeroext for integer arguments on LoongArch64 2024-10-23 04:42:21 +02:00
Asuna
6b65524620 Set signext or zeroext for integer arguments on RISC-V 2024-10-23 04:42:03 +02:00
Asuna
03df13b70d Introduce adjust_for_rust_abi in rustc_target 2024-10-23 03:21:59 +02:00
bors
bca5fdebe0 Auto merge of #131321 - RalfJung:feature-activation, r=nnethercote
terminology: #[feature] *enables* a feature (instead of "declaring" or "activating" it)

Mostly, we currently call a feature that has a corresponding `#[feature(name)]` attribute in the current crate a "declared" feature. I think that is confusing as it does not align with what "declaring" usually means. Furthermore, we *also* refer to `#[stable]`/`#[unstable]` as *declaring* a feature (e.g. in [these diagnostics](f25e5abea2/compiler/rustc_passes/messages.ftl (L297-L301))), which aligns better with what "declaring" usually means. To make things worse, the functions  `tcx.features().active(...)` and  `tcx.features().declared(...)` both exist and they are doing almost the same thing (testing whether a corresponding `#[feature(name)]`  exists) except that `active` would ICE if the feature is not an unstable lang feature. On top of this, the callback when a feature is activated/declared is called `set_enabled`, and many comments also talk about "enabling" a feature.

So really, our terminology is just a mess.

I would suggest we use "declaring a feature" for saying that something is/was guarded by a feature (e.g. `#[stable]`/`#[unstable]`), and "enabling a feature" for  `#[feature(name)]`. This PR implements that.
2024-10-22 11:02:35 +00:00
Ralf Jung
46ce5cbf33 terminology: #[feature] *enables* a feature (instead of "declaring" or "activating" it) 2024-10-22 07:37:54 +01:00
bors
f225713007 Auto merge of #132020 - workingjubilee:rollup-a8iehqg, r=workingjubilee
Rollup of 6 pull requests

Successful merges:

 - #130432 (rust_for_linux: -Zregparm=<N> commandline flag for X86 (#116972))
 - #131697 (`rt::Argument`: elide lifetimes)
 - #131807 (Always specify `llvm_abiname` for RISC-V targets)
 - #131954 (shave 150ms off bootstrap)
 - #132015 (Move const trait tests from `ui/rfcs/rfc-2632-const-trait-impl` to `ui/traits/const-traits`)
 - #132017 (Update triagebot.toml)

r? `@ghost`
`@rustbot` modify labels: rollup
2024-10-22 05:49:18 +00:00
Jubilee
1b24c6fc14
Rollup merge of #131807 - beetrees:riscv-target-abi, r=workingjubilee
Always specify `llvm_abiname` for RISC-V targets

For RISC-V targets, when `llvm_abiname` is not specified LLVM will infer the ABI from the target features, causing #116344 to occur. This PR adds the correct `llvm_abiname` to all RISC-V targets where it is missing (which are all soft-float targets), and adds a test to prevent future RISC-V targets from accidentally omitting `llvm_abiname`. The only affect of this PR is that `-Ctarget-feature=+f` (or similar) will no longer affect the ABI on the modified targets.

<!-- homu-ignore:start -->
r? `@RalfJung`
<!--- homu-ignore:end -->
2024-10-21 20:32:01 -07:00
Jubilee
fe2cbbd2d5
Rollup merge of #130432 - azhogin:azhogin/regparm, r=workingjubilee,pnkfelix
rust_for_linux: -Zregparm=<N> commandline flag for X86 (#116972)

Command line flag `-Zregparm=<N>` for X86 (32-bit) for rust-for-linux: https://github.com/rust-lang/rust/issues/116972
Implemented in the similar way as fastcall/vectorcall support (args are marked InReg if fit).
2024-10-21 20:32:00 -07:00
Ralf Jung
de3cbf3c56 make unsupported_calling_conventions a hard error 2024-10-20 15:22:21 +02:00
Stuart Cook
0bfc49b053
Rollup merge of #131876 - workingjubilee:llvm-c-c-c-comdat, r=Zalathar
compiler: Use LLVM's Comdat support

Acting on these long-ago issues:
- https://github.com/rust-lang/rust/issues/46437
- https://github.com/rust-lang/rust/issues/68955
2024-10-20 14:06:03 +11:00
Jubilee Young
45d61b0d26 cg_llvm: Reuse LLVM-C Comdat support
Migrate `llvm::set_comdat` and `llvm::SetUniqueComdat` to LLVM-C FFI.

Note, now we can call `llvm::set_comdat` only when the target actually
supports adding comdat. As this has no convenient LLVM-C API, we
implement this as `TargetOptions::supports_comdat`.

Co-authored-by: Stuart Cook <Zalathar@users.noreply.github.com>
2024-10-19 10:46:10 -07:00
Jubilee Young
b9c96780b4 compiler: Revert -Zregparm handling for extern Rust 2024-10-18 11:59:20 -07:00
WANG Rui
275ec06900 Default to the medium code model on OpenHarmony LoongArch target
The context for this is #130266: setting the medium code model for the
'loongarch64-linux-ohos' target.
2024-10-18 14:16:51 +08:00
Andrew Zhogin
b3ae64d24f rust_for_linux: -Zregparm=<N> commandline flag for X86 (#116972) 2024-10-18 00:29:31 +07:00
WANG Rui
67ed9fac55 Enable XRay instrumentation for LoongArch Linux targets 2024-10-17 22:35:51 +08:00
Matthias Krüger
9aee5d98cf
Rollup merge of #131583 - heiher:loong-issue-118053, r=jieyouxu
Setting up indirect access to external data for loongarch64-linux-{musl,ohos}

In issue #118053, the `loongarch64-unknown-linux-gnu` target needs indirection to access external data, and so do the `loongarch64-unknown-linux-musl` and `loongarch64-unknown-linux-ohos` targets.
2024-10-17 12:07:20 +02:00
beetrees
3ea91c05db
Always specify llvm_abiname for RISC-V targets 2024-10-17 02:07:02 +01:00
Kajetan Puchalski
f641c32aad rustc_target: Add pauth-lr aarch64 target feature
Add the pauth-lr target feature, corresponding to aarch64 FEAT_PAuth_LR.
This feature has been added in LLVM 19.
It is currently not supported by the Linux hwcap and so we cannot add
runtime feature detection for it at this time.
2024-10-16 18:00:51 +01:00
Matthew Maurer
e985396145 llvm: Match aarch64 data layout to new LLVM layout
LLVM has added 3 new address spaces to support special Windows use
cases. These shouldn't trouble us for now, but LLVM requires matching
data layouts.

See llvm/llvm-project#111879 for details
2024-10-16 01:16:44 +00:00
Matthias Krüger
dbb0581ff5
Rollup merge of #131667 - taiki-e:aarch64-inline-asm-reg-emit, r=Amanieu
Fix AArch64InlineAsmReg::emit

Currently, this method uses `self as u32 - Self::x0 as u32` to get register index:
36780360b6/compiler/rustc_target/src/asm/aarch64.rs (L204)

However, this is incorrect for reasons explained in the following comment:
36780360b6/compiler/rustc_codegen_llvm/src/asm.rs (L544-L549)

r? ``@Amanieu``

``@rustbot`` label O-AArch64 +A-inline-assembly
2024-10-14 17:06:38 +02:00
Matthias Krüger
43bf4f1fd3
Rollup merge of #131332 - taiki-e:arm64ec-clobber-abi, r=Amanieu
Fix clobber_abi and disallow SVE-related registers in Arm64EC inline assembly

Currently `clobber_abi` in Arm64EC inline assembly is implemented using `InlineAsmClobberAbi::AArch64NoX18`, but broken since it attempts to clobber registers that cannot be used in Arm64EC: https://godbolt.org/z/r3PTrGz5r

```
error: cannot use register `x13`: x13, x14, x23, x24, x28, v16-v31 cannot be used for Arm64EC
 --> <source>:6:14
  |
6 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
  |              ^^^^^^^^^^^^^^^^

error: cannot use register `x14`: x13, x14, x23, x24, x28, v16-v31 cannot be used for Arm64EC
 --> <source>:6:14
  |
6 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
  |              ^^^^^^^^^^^^^^^^

<omitted the same errors for v16-v31>
```

Additionally, this disallows SVE-related registers per https://github.com/rust-lang/rust/pull/131332#issuecomment-2401189142.

cc ``@dpaoliello``

r? ``@Amanieu``

``@rustbot`` label O-windows O-AArch64 +A-inline-assembly
2024-10-14 17:06:35 +02:00
Matthias Krüger
cb140dcb00
Rollup merge of #131473 - workingjubilee:move-that-abi-up, r=saethlin
compiler: `{TyAnd,}Layout` comes home

The `Layout` and `TyAndLayout` types are heavily abstract and have no particular target-specific qualities, though we do use them to answer questions particular to targets. We can keep it that way if we simply move them out of `rustc_target` and into `rustc_abi`. They bring a small entourage of connected types with them, but that's fine.

This will allow us to strengthen a few abstraction barriers over time and thus make the notoriously gnarly layout code easier to refactor. For now, we don't need to worry about that and deliberately use reexports to minimize this particular diff.
2024-10-14 06:04:28 +02:00
Taiki Endo
67ebb6c20b Fix AArch64InlineAsmReg::emit 2024-10-14 06:04:07 +09:00
Taiki Endo
d858dfedbb Fix clobber_abi and disallow SVE-related registers in Arm64EC inline assembly 2024-10-14 05:30:45 +09:00
WANG Rui
b1579e8acf Setting up indirect access to external data for loongarch64-linux-{musl,ohos}
In issue #118053, the `loongarch64-unknown-linux-gnu` target needs indirection
to access external data, and so do the `loongarch64-unknown-linux-musl` and
`loongarch64-unknown-linux-ohos` targets.
2024-10-13 18:56:35 +08:00
Trevor Gross
d576cdda7e
Rollup merge of #131334 - heiher:loong-sanitizers, r=Mark-Simulacrum
Enable sanitizers for loongarch64-unknown-*

Enable sanitizers for `loongarch64-unknown-linux-{gnu,musl,ohos}` targets.
2024-10-12 21:38:35 -05:00
Trevor Gross
9e72070f77
Rollup merge of #131310 - taiki-e:msp430-clobber-abi, r=Amanieu
Support clobber_abi in MSP430 inline assembly

This supports `clobber_abi` which is one of the requirements of stabilization mentioned in #93335.

Refs: Section 3.2 "Register Conventions" in [MSP430 Embedded Application Binary Interface](https://www.ti.com/lit/an/slaa534a/slaa534a.pdf)

cc ``@cr1901``

r? ``@Amanieu``

``@rustbot`` label +O-msp430
2024-10-11 23:57:46 -04:00
Jubilee Young
10721909f2 compiler: Wire {TyAnd,}Layout into rustc_abi
This finally unites TyAndLayout, Layout, and LayoutS into the same crate,
as one might imagine they would be placed. No functional changes.
2024-10-11 17:41:52 -07:00
Jubilee Young
255bdd2f24 compiler: Empty out rustc_target::abi 2024-10-11 17:41:52 -07:00
Jubilee Young
559de74562 compiler: Move impl of ToJson for abi::Endian 2024-10-11 17:41:52 -07:00
Matthias Krüger
fc81a7c1d5
Rollup merge of #131208 - mustartt:aix-call-abi, r=davidtwco
ABI: Pass aggregates by value on AIX

On AIX we pass aggregates byval. Adds new ABI for AIX for powerpc64.

313ad85dfa/clang/lib/CodeGen/Targets/PPC.cpp (L216)

Fixes the following 2 testcases on AIX:
```
tests/ui/abi/extern/extern-pass-TwoU16s.rs
tests/ui/abi/extern/extern-pass-TwoU8s.rs
```
2024-10-11 15:36:51 +02:00
Kajetan Puchalski
335f67b652 rustc_target: Add sme-b16b16 as an explicit aarch64 target feature
LLVM 20 split out what used to be called b16b16 and correspond to aarch64
FEAT_SVE_B16B16 into sve-b16b16 and sme-b16b16.
Add sme-b16b16 as an explicit feature and update the codegen accordingly.
2024-10-10 10:24:57 +00:00
Jubilee Young
43e198a3ae compiler: Seal off the rustc_target::abi enum glob imports 2024-10-08 18:24:56 -07:00
Stuart Cook
e416a9cf4e
Rollup merge of #131170 - madsmtm:target-info-esp32-vendor, r=workingjubilee
Fix `target_vendor` in non-IDF Xtensa ESP32 targets

`rustc`'s Xtensa ESP32 targets are the following:
- `xtensa-esp32-none-elf`
- `xtensa-esp32-espidf`
- `xtensa-esp32s2-none-elf`
- `xtensa-esp32s2-espidf`
- `xtensa-esp32s3-none-elf`
- `xtensa-esp32s3-espidf`

The ESP-IDF targets already set `target_vendor="espressif"`, however, the ESP32 is, from my understanding, produced by Espressif regardless of whether using the IDF or not, so we should set the target vendor there as well?
2024-10-08 13:19:43 +11:00
WANG Rui
8a5e03bf43 Enable sanitizers for loongarch64-unknown-* 2024-10-06 11:57:06 +08:00
Taiki Endo
3743618c13 Support clobber_abi in MSP430 inline assembly 2024-10-06 08:14:44 +09:00
Henri Lunnikivi
04099b663c Update target fns to latest main 2024-10-05 12:14:35 +03:00