Commit Graph

1751 Commits

Author SHA1 Message Date
Matthias Krüger
32574153d9
Rollup merge of #138426 - madsmtm:vita-llvm-target, r=jieyouxu
Fix `armv7-sony-vita-newlibeabihf` LLVM target triple

It was previously normalized by LLVM to `thumbv7a-vita-unknown-eabihf` (can be seen with `clang -target thumbv7a-vita-eabihf -v`), which seems wrong, as Vita is the OS name.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

CC target maintainers ``@nikarh,`` ``@pheki`` and ``@ZetaNumbers.``
r? jieyouxu
2025-03-31 23:05:43 +02:00
bors
b9ea82b84a Auto merge of #137836 - madsmtm:openwrt-target-vendor, r=jieyouxu
Set `target_vendor = "openwrt"` on `mips64-openwrt-linux-musl`

OpenWRT is a Linux distribution for embedded network devices. The target name contains `openwrt`, so we should set `cfg(target_vendor = "openwrt")`.

This is similar to what other Linux distributions do (the only one in-tree is `x86_64-unikraft-linux-musl`, but that sets `target_vendor = "unikraft"`).

Motivation: To make correctly [parsing target names](https://github.com/rust-lang/cc-rs/pull/1413) simpler.

Fixes https://github.com/rust-lang/rust/issues/131165.

CC target maintainer `@Itus-Shield`
2025-03-30 08:33:29 +00:00
bors
85f518ec8e Auto merge of #138742 - taiki-e:riscv-vector, r=Amanieu
rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check

Currently, we have only unstable `v` target feature, but RISC-V have more vector-related extensions. The first commit of this PR adds them to unstable `riscv_target_feature`.

- `unaligned-vector-mem`: Has reasonably performant unaligned vector
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L1379)
  - Similar to currently unstable `unaligned-scalar-mem` target feature, but for vector instructions.
- `zvfh`: Vector Extension for Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfh-vector-extension-for-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L668)
  - This implies `zvfhmin` and `zfhmin`
- `zvfhmin`: Vector Extension for Minimal Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L662)
  - This implies `zve32f`
- `zve32x`, `zve32f`, `zve64x`, `zve64f`, `zve64d`: Vector Extensions for Embedded Processors
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zve-vector-extensions-for-embedded-processors)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L612-L641)
  - `zve32x` implies `zvl32b`
  - `zve32f` implies `zve32x` and `f`
  - `zve64x` implies `zve32x` and `zvl64b`
  - `zve64f` implies `zve32f` and `zve64x`
  - `zve64d` implies `zve64f` and `d`
  - `v` implies `zve64d`
- `zvl*b`: Minimum Vector Length Standard Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvl-minimum-vector-length-standard-extensions)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L600-L610)
  - `zvl{N}b` implies `zvl{N>>1}b`
  - `v` implies `zvl128b`
- Vector Cryptography and Bit-manipulation Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/vector-crypto.adoc)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L679-L807)
  - `zvkb`: Vector Bit-manipulation used in Cryptography
    - This implies `zve32x`
  - `zvbb`: Vector basic bit-manipulation instructions
    - This implies `zvkb`
  - `zvbc`: Vector Carryless Multiplication
    - This implies `zve64x`
  - `zvkg`: Vector GCM instructions for Cryptography
    - This implies `zve32x`
  - `zvkned`: Vector AES Encryption & Decryption (Single Round)
    - This implies `zve32x`
  - `zvknha`: Vector SHA-2 (SHA-256 only))
    - This implies `zve32x`
  - `zvknhb`: Vector SHA-2 (SHA-256 and SHA-512)
    - This implies `zve64x`
    - This is superset of `zvknha`, but doesn't imply that feature at least in LLVM
  - `zvksed`: SM4 Block Cipher Instructions
    - This implies `zve32x`
  - `zvksh`: SM3 Hash Function Instructions
    - This implies `zve32x`
  - `zvkt`: Vector Data-Independent Execution Latency
    - Similar to already stabilized scalar cryptography extension `zkt`.
  - `zvkn`: Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zkn`.
  - `zvknc`: Shorthand for 'Zvkn' and 'Zvbc'
  - `zvkng`: shorthand for 'Zvkn' and 'Zvkg'
  - `zvks`: shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zks`.
  - `zvksc`: shorthand for 'Zvks' and 'Zvbc'
  - `zvksg`: shorthand for 'Zvks' and 'Zvkg'

Also, our vector ABI check wants `zvl*b` target features, the second commit of this PR updates vector ABI check to use them.

4e2b096ed6/compiler/rustc_target/src/target_features.rs (L707-L708)

---

r? `@Amanieu`

`@rustbot` label +O-riscv +A-target-feature
2025-03-30 02:21:56 +00:00
Matthias Krüger
2b0c2f7904
Rollup merge of #138431 - madsmtm:uclibc-llvm-target, r=jieyouxu
Fix `uclibc` LLVM target triples

`uclibc` is not an environment understood by LLVM, it is only a concept in Clang that can be selected with `-muclibc` (it affects which dynamic linker is passed to the static linker's `-dynamic-linker` flag).

In fact, using `uclibcgnueabi`/`uclibc` is actively harmful, as it prevents LLVM from seeing that the target is gnu-like; we should use `gnueabi`/`gnu` directly instead.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

**There are no target maintainers for these targets.** So I'll CC ``@lancethepants`` and ``@skrap`` who maintain the related `armv7-unknown-linux-uclibceabi` and `armv7-unknown-linux-uclibceabihf` (both of which already pass `-gnu` instead of `-uclibc`) in case they have any insights.

r? jieyouxu
2025-03-29 21:08:11 +01:00
bors
068609ce76 Auto merge of #138601 - RalfJung:wasm-abi-fcw, r=alexcrichton
add FCW to warn about wasm ABI transition

See https://github.com/rust-lang/rust/issues/122532 for context: the "C" ABI on wasm32-unk-unk will change. The goal of this lint is to warn about any function definition and calls whose behavior will be affected by the change. My understanding is the following:
- scalar arguments are fine
  - including 128 bit types, they get passed as two `i64` arguments in both ABIs
- `repr(C)` structs (recursively) wrapping a single scalar argument are fine (unless they have extra padding due to over-alignment attributes)
- all return values are fine

`@bjorn3` `@alexcrichton` `@Manishearth` is that correct?

I am making this a "show up in future compat reports" lint to maximize the chances people become aware of this. OTOH this likely means warnings for most users of Diplomat so maybe we shouldn't do this?

IIUC, wasm-bindgen should be unaffected by this lint as they only pass scalar types as arguments.

Tracking issue: https://github.com/rust-lang/rust/issues/138762
Transition plan blog post: https://github.com/rust-lang/blog.rust-lang.org/pull/1531

try-job: dist-various-2
2025-03-26 00:06:46 +00:00
Ralf Jung
072ccce553 make -Zwasm-c-abi=legacy suppress the lint 2025-03-25 08:22:35 +01:00
Ralf Jung
c961d123d2 add FCW to warn about wasm ABI transition 2025-03-25 08:22:35 +01:00
Takayuki Maeda
e9a528c9b5
Rollup merge of #138701 - tvladyslav:serializable_default_codegen_backend, r=workingjubilee
Make default_codegen_backend serializable

This PR makes default_codegen_backend serializable.
2025-03-25 15:36:33 +09:00
Ralf Jung
b2d7271858 target spec check: better error when llvm-floatabi is missing 2025-03-21 16:08:48 +01:00
Taiki Endo
8a6f96a4a0 rustc_target: Use zvl*b target features in vector ABI check 2025-03-20 19:48:02 +09:00
Taiki Endo
55add8fce3 rustc_target: Add more RISC-V vector-related features 2025-03-20 19:47:57 +09:00
Vladyslav Tsilytskyi
39efa7c590 Make default_codegen_backend serializable 2025-03-19 12:35:18 +01:00
Matthias Krüger
aa53a72dff
Rollup merge of #138608 - heiher:issue-116344, r=RalfJung
rustc_target: Add target feature constraints for LoongArch

Part of https://github.com/rust-lang/rust/issues/116344

r? `@RalfJung`
2025-03-17 22:49:07 +01:00
WANG Rui
0ee99cf240 rustc_target: Add target feature constraints for LoongArch
Part of https://github.com/rust-lang/rust/issues/116344
2025-03-17 22:45:35 +08:00
Jacob Pratt
b3b7a3b8d2
Rollup merge of #137621 - Berrysoft:cygwin-std, r=joboet
Add std support to cygwin target
2025-03-17 05:47:49 -04:00
León Orell Valerian Liehr
10055fb03a
Rollup merge of #138056 - heiher:loong64v1.1-features, r=petrochenkov
rustc_target: Add target features for LoongArch v1.1

This patch adds new target features for LoongArch v1.1:

* div32
* lam-bh
* lamcas
* ld-seq-sa
* scq
2025-03-15 00:18:22 +01:00
Jacob Pratt
459352a217
Rollup merge of #136892 - erickt:fuchsia-target, r=jieyouxu
Sync Fuchsia target spec with clang Fuchsia driver

This updates the Fuchsia target spec with the [Clang Fuchsia driver], which picks up a few changes:

* Adds `-z start-stop-visibility=hidden` and `-z rel` to the pre link arguments.
* Adds `--execute-only` and `--fix-cortex-a53-843419` for `aarch64-unknown-fuchsia`.
* Enables the equivalent cpu features for `x86-64-v2` for `x86_64-unknown-fuchsia`, which is our minimum supported x86_64 platform according to [RFC-0073].

try-job: x86_64-fuchsia

[Clang Fuchsia driver]: 8374d42186/clang/lib/Driver/ToolChains/Fuchsia.cpp
[RFC-0073]: https://fuchsia.dev/fuchsia-src/contribute/governance/rfcs/0073_x86_64_platform_requirement
2025-03-14 01:37:29 -04:00
WANG Rui
d989bf5bbe rustc_target: Add target features for LoongArch v1.1 2025-03-14 09:52:02 +08:00
Matthias Krüger
69b3ad18d2
Rollup merge of #138427 - madsmtm:vxworks-llvm-target, r=jieyouxu
Fix RISC-V VxWorks LLVM target triples

The targets `riscv32-wrs-vxworks` and `riscv64-wrs-vxworks` uses the plain `$ARCH` LLVM triple, which LLVM normalizes to `$ARCH-unknown-unknown`, we should use `$ARCH-unknown-linux-gnu$ABI` which is consistent with the the other VxWorks targets.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

Alternative: Pass `$ARCH-unknown-none` in the other VxWorks LLVM triples, I don't know anything about VxWorks, so am unsure which is the most correct option.

CC target maintainer `@biabbas.`
r? jieyouxu
2025-03-13 17:44:12 +01:00
Mads Marquart
eab700a0aa Fix uclibc LLVM target triples
`uclibc` is not an environment understood by LLVM, it is only a concept
in Clang that can be selected with `-muclibc` (it affects which dynamic
linker is passed to the static linker's `-dynamic-linker` flag).

In fact, using `uclibcgnueabi`/`uclibc` is actively harmful, as it
prevents LLVM from seeing that the target is gnu-like; we should use
`gnueabi`/`gnu` directly instead.
2025-03-12 23:40:25 +01:00
Mads Marquart
65bd61d2fb Fix armv7-sony-vita-newlibeabihf LLVM target triple
It was previously normalized by LLVM to `thumbv7a-vita-unknown-eabihf`,
which is probably wrong, as Vita is the OS.
2025-03-12 22:44:59 +01:00
Mads Marquart
0434013a6e Fix RISC-V VxWorks LLVM target triples
The targets used the plain `$ARCH` triple, which LLVM normalizes to
`$ARCH-unknown-unknown`, which is inconsistent with the the other
VxWorks targets which all use `$ARCH-unknown-linux-gnu$ABI`.
2025-03-12 22:42:17 +01:00
Matthias Krüger
d93ef397ce
Rollup merge of #138331 - nnethercote:use-RUSTC_LINT_FLAGS-more, r=onur-ozkan,jieyouxu
Use `RUSTC_LINT_FLAGS` more

An alternative to the failed #138084.

Fixes #138106.

r? ````@jieyouxu````
2025-03-12 17:59:08 +01:00
bors
ebf0cf75d3 Auto merge of #137586 - nnethercote:SetImpliedBits, r=bjorn3
Speed up target feature computation

The LLVM backend calls `LLVMRustHasFeature` twice for every feature. In short-running rustc invocations, this accounts for a surprising amount of work.

r? `@bjorn3`
2025-03-11 12:05:16 +00:00
Nicholas Nethercote
ff0a5fe975 Remove #![warn(unreachable_pub)] from all compiler/ crates.
It's no longer necessary now that `-Wunreachable_pub` is being passed.
2025-03-11 13:14:21 +11:00
Arjun Ramesh
336a327f7c Target definition for wasm32-wali-linux-musl to support the Wasm Linux
Interface

This commit does not patch libc, stdarch, or cc
2025-03-10 21:26:45 -04:00
王宇逸
886fb15c0f Update metadata for cygwin target 2025-03-10 21:23:31 +08:00
许杰友 Jieyou Xu (Joe)
063ef18fdc Revert "Use workspace lints for crates in compiler/ #138084"
Revert <https://github.com/rust-lang/rust/pull/138084> to buy time to
consider options that avoids breaking downstream usages of cargo on
distributed `rustc-src` artifacts, where such cargo invocations fail due
to inability to inherit `lints` from workspace root manifest's
`workspace.lints` (this is only valid for the source rust-lang/rust
workspace, but not really the distributed `rustc-src` artifacts).

This breakage was reported in
<https://github.com/rust-lang/rust/issues/138304>.

This reverts commit 48caf81484, reversing
changes made to c6662879b2.
2025-03-10 18:12:47 +08:00
Matthias Krüger
48caf81484
Rollup merge of #138084 - nnethercote:workspace-lints, r=jieyouxu
Use workspace lints for crates in `compiler/`

This is nicer and hopefully less error prone than specifying lints via bootstrap.

r? ``@jieyouxu``
2025-03-09 10:34:50 +01:00
Jacob Pratt
8cac259347
Rollup merge of #137957 - Noratrieb:no, r=wesleywiser
Remove i586-pc-windows-msvc

See [MCP 840](https://github.com/rust-lang/compiler-team/issues/840).

I left a specialized error message that should help users that hit this in the wild (for example, because they use it in their CI).

```
error: Error loading target specification: the `i586-pc-windows-msvc` target has been removed. Use the `i686-pc-windows-msvc` target instead.
       Windows 10 (the minimum required OS version) requires a CPU baseline of at least i686 so you can safely switch. Run `rustc --print target-list` for a list of built-in targets
```

``@workingjubilee`` ``@calebzulawski`` fyi portable-simd uses this target in CI, if you wanna remove it already before this happens
2025-03-07 21:57:50 -05:00
Jacob Pratt
3b595aa13f
Rollup merge of #137363 - workingjubilee:untangle-x86-abi-impl, r=jieyouxu
compiler: factor Windows x86-32 ABI impl into its own file

While it shares more than zero code with the SysV x86-32 ABI impl, there is no particular reason to organize wildly different ABIs using if-else in the same function.
2025-03-07 21:57:48 -05:00
Nicholas Nethercote
8a3e03392e Remove #![warn(unreachable_pub)] from all compiler/ crates.
(Except for `rustc_codegen_cranelift`.)

It's no longer necessary now that `unreachable_pub` is in the workspace
lints.
2025-03-08 08:41:43 +11:00
Nicholas Nethercote
beba32cebb Specify rust lints for compiler/ crates via Cargo.
By naming them in `[workspace.lints.rust]` in the top-level
`Cargo.toml`, and then making all `compiler/` crates inherit them with
`[lints] workspace = true`. (I omitted `rustc_codegen_{cranelift,gcc}`,
because they're a bit different.)

The advantages of this over the current approach:
- It uses a standard Cargo feature, rather than special handling in
  bootstrap. So, easier to understand, and less likely to get
  accidentally broken in the future.
- It works for proc macro crates.

It's a shame it doesn't work for rustc-specific lints, as the comments
explain.
2025-03-08 08:41:09 +11:00
Jubilee Young
9d8ce72901 compiler: factor Windows x86-32 ABI impl into its own file
While it shares more than zero code with the SysV x86-32 ABI impl,
there is no particular reason to organize wildly different ABIs
using if-else in the same function.
2025-03-05 15:11:20 -08:00
Sergio Gasquez
376955ef25 feat: Remove - from xtensa targets cpu names
Co-authored-by: MabezDev <scott@mabez.dev>
2025-03-05 16:34:09 +01:00
Nicholas Nethercote
2df8e657f2 Simplify implied_target_features.
Currently its argument is an iterator, but in practice it's always a
singleton.
2025-03-05 09:20:28 +11:00
bors
f9e0239a7b Auto merge of #135695 - Noratrieb:elf-raw-dylib, r=bjorn3
Support raw-dylib link kind on ELF

raw-dylib is a link kind that allows rustc to link against a library without having any library files present.
This currently only exists on Windows. rustc will take all the symbols from raw-dylib link blocks and put them in an import library, where they can then be resolved by the linker.

While import libraries don't exist on ELF, it would still be convenient to have this same functionality. Not having the libraries present at build-time can be convenient for several reasons, especially cross-compilation. With raw-dylib, code linking against a library can be cross-compiled without needing to have these libraries available on the build machine. If the libc crate makes use of this, it would allow cross-compilation without having any libc available on the build machine. This is not yet possible with this implementation, at least against libc's like glibc that use symbol versioning. The raw-dylib kind could be extended with support for symbol versioning in the future.

This implementation is very experimental and I have not tested it very well. I have tested it for a toy example and the lz4-sys crate, where it was able to successfully link a binary despite not having a corresponding library at build-time.

I was inspired by Björn's comments in https://internals.rust-lang.org/t/bundle-zig-cc-in-rustup-by-default/22096/27
Tracking issue: #135694

r? bjorn3

try-job: aarch64-apple
try-job: x86_64-msvc-1
try-job: x86_64-msvc-2
try-job: test-various
2025-03-04 15:39:44 +00:00
Noratrieb
b5562c04e7 Remove i586-pc-windows-msvc
See MCP 840.

I left a specialized error message that should help users that hit this
in the wild (for example, because they use it in their CI).
2025-03-03 20:15:25 +01:00
Matthias Krüger
1762f018f7
Rollup merge of #137860 - taiki-e:powerpcspe-msync, r=workingjubilee
rustc_target: Add msync target feature and enable it on powerpcspe targets

Some older PowerPC processors do not have the `sync` (`sync 0`) and `lwsync` (`sync 1`) instructions, but instead have the `msync` instruction. (IIRC `msync` and `sync` will be assembled into the same bit-pattern, but `lwsync` will be SIGILL. See also https://gcc.gnu.org/legacy-ml/gcc-patches/2006-11/msg01238.html.)

LLVM recognizes this as the [`msync` feature](cc5d8a4b2f/llvm/lib/Target/PowerPC/PPC.td (L140)) and enables for some cpus such as [e500](cc5d8a4b2f/llvm/lib/Target/PowerPC/PPC.td (L644)).

powerpcspe is a target for CPUs such as e500 ([Debian Wiki](https://wiki.debian.org/PowerPCSPEPort)). However, the `msync` feature is currently not enabled except for vxworks, and at least since 2022-04, powerpc-unknown-linux-gnuspe was known to not work on real hardware without `-C target-cpu` (e.g., #96394, #117361).

8c392966a0/compiler/rustc_target/src/spec/targets/powerpc_wrs_vxworks_spe.rs (L28)

Fixes #117361

cc `@BKPepe` ([powerpc-unknown-linux-muslspe target maintainer](https://doc.rust-lang.org/nightly/rustc/platform-support/powerpc-unknown-linux-muslspe.html#target-maintainers))
cc `@glaubitz` (who added powerpc-unknown-linux-gnuspe in https://github.com/rust-lang/rust/pull/48484)
cc `@th0ma7` (who opened #117361)

r? workingjubilee

`@rustbot` label +O-PowerPC +A-target-feature
2025-03-02 22:44:25 +01:00
Taiki Endo
6f7fd11474 rustc_target: Add msync target feature and enable it on powerpcspe targets 2025-03-02 03:03:52 +09:00
Mads Marquart
c4d642616d Set target_vendor = "openwrt"
On mips64-openwrt-linux-musl target.
2025-03-01 04:51:03 +01:00
Ralf Jung
aac65f562b rename BackendRepr::Vector → SimdVector 2025-02-28 17:17:45 +01:00
Noratrieb
a954c51280 Support raw-dylib link kind on ELF
raw-dylib is a link kind that allows rustc to link against a library
without having any library files present.
This currently only exists on Windows. rustc will take all the symbols
from raw-dylib link blocks and put them in an import library, where they
can then be resolved by the linker.

While import libraries don't exist on ELF, it would still be convenient
to have this same functionality. Not having the libraries present at
build-time can be convenient for several reasons, especially
cross-compilation. With raw-dylib, code linking against a library can be
cross-compiled without needing to have these libraries available on the
build machine. If the libc crate makes use of this, it would allow
cross-compilation without having any libc available on the build
machine. This is not yet possible with this implementation, at least
against libc's like glibc that use symbol versioning.
The raw-dylib kind could be extended with support for symbol versioning
in the future.

This implementation is very experimental and I have not tested it very
well. I have tested it for a toy example and the lz4-sys crate, where it
was able to successfully link a binary despite not having a
corresponding library at build-time.
2025-02-26 19:09:51 +01:00
León Orell Valerian Liehr
e02de837be
Rollup merge of #137370 - RalfJung:x86-abi-fallback, r=SparrowLii
adjust_abi: make fallback logic for ABIs a bit easier to read

I feel like the match guards here make this unnecessarily harder to follow.
2025-02-25 13:07:23 +01:00
Michael Goulet
828a3a41b3
Rollup merge of #137417 - taiki-e:riscv-atomic, r=Amanieu
rustc_target: Add more RISC-V atomic-related features

This is a continuation of https://github.com/rust-lang/rust/pull/130877 and adds a few target features, including `zacas`, which was experimental in LLVM 19 and marked non-experimental in LLVM 20.

This adds the following target features to unstable riscv_target_feature:

- `za64rs` (Za64rs Extension 1.0): Reservation Set Size of at Most 64 Bytes
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L227-L228), [available since LLVM 18](8649328060))
- `za128rs` (Za128rs Extension 1.0): Reservation Set Size of at Most 128 Bytes
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L230-L231), [available since LLVM 18](8649328060))
  - IIUC, `za*rs` can be referenced when implementing helpers to reduce contention in synchronization primitives, like [`crossbeam_utils::CachePadded`](https://docs.rs/crossbeam-utils/latest/crossbeam_utils/struct.CachePadded.html). (relevant discussion: https://github.com/riscv/riscv-profiles/issues/79)
- `zacas` (Zacas Extension 1.0): Atomic Compare-And-Swap Instructions (`amocas.{w,d,q}{,.aq,.rl,.aqrl}` and `amocas.{b,h}{,.aq,.rl,.aqrl}` when `zabha` is also enabled)
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L240-L243), [available as non-experimental since LLVM 20](614aeda93b))
  - This implies `zaamo`.
  - This is used to optimize CAS in existing atomics and/or implement 64-bit/128-bit atomics on riscv32/riscv64 (e.g., https://github.com/taiki-e/portable-atomic/pull/173).
  - Note that [LLVM does not automatically use this instruction for 64-bit/128-bit atomics on riscv32/riscv64 even if this feature is enabled, because doing it changes the ABI](876174ffd7/llvm/docs/RISCVUsage.rst (riscv-zacas-note)). (If the ability to do that is provided by LLVM in the future, it should probably be controlled by another ABI feature similar to `forced-atomics`.)
- `zama16b` (Zama16b Extension 1.0): Atomic 16-byte misaligned loads, stores and AMOs
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L255-L256), [available since LLVM 19](b090569685))
  - IIUC, unlike AArch64 FEAT_LSE2 which also makes 16-byte aligned ldp ({i,u}128 load) atomic, this extension only affects instructions that already considered atomic if they were naturally aligned. i.e., fld (f64 load) on riscv32 would not be atomic with or without this extension ([relevant QEMU code](b69801dd6b/target/riscv/insn_trans/trans_rvd.c.inc (L50-L62))).
- `zawrs` (Zawrs Extension 1.0): Wait on Reservation Set (`wrs.nto` and `wrs.sto`)
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L258), [available as non-experimental since LLVM 17](d41a73aa94))
  - This is used to optimize synchronization primitives (e.g., Linux uses this for spinlocks (b8ddb0df30)).

Btw, the question of whether `zaamo` is implied by `zabha` or not, which was discussed in https://github.com/rust-lang/rust/pull/130877, has been resolved in LLVM 20, since LLVM now treats `zaamo` as implied by `zabha`/`zacas` (https://github.com/llvm/llvm-project/pull/115694), just like GCC and rustc.

r? `@Amanieu`

`@rustbot` label +O-riscv +A-target-feature
2025-02-24 19:21:47 -05:00
Trevor Gross
2c6fa32bdc
Rollup merge of #136637 - Pyr0de:binary-format, r=Noratrieb
Add binary_format to rustc target specs

Added binary format field to `TargetOptions`

Fixes #135724

r? `@Noratrieb`
2025-02-23 14:30:26 -05:00
Taiki Endo
a343dcb97f rustc_target: Add more RISC-V atomic-related features 2025-02-22 16:15:14 +09:00
Michael Goulet
76d341fa09 Upgrade the compiler to edition 2024 2025-02-22 00:01:48 +00:00
Matthias Krüger
e67d4499a6
Rollup merge of #135630 - folkertdev:s390x-target-features, r=Amanieu
add more `s390x` target features

Closes #88937

tracking issue: https://github.com/rust-lang/rust/issues/130869

The target feature names are, right now, just the llvm target feature names. These mostly line up well with the names of [Facility Indications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel (and `/proc/cpuinfo`) uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.

There are a number of implied target features between the vector facilities (based on the [Facility Indications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):

- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.

The remaining facilities do not have any implied target features (that we provide):

- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.

The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](d49a2d2bc9/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.

I'll also update the `is_s390x_feature_supported` macro (added in https://github.com/rust-lang/stdarch/pull/1699, not yet on nightly, that needs an stdarch sync) to include these target features.

``@Amanieu`` you had some reservations about the `"vector"` target feature name. It does appear to be the most "official" name we have. On the one hand the name is very generic, and some of the other names are rather long. For the `neural-network-processing-assist` even LLVM thought that was a bit much and shortened it to `nnp-assist`. Also for `vector-packed-decimal-enhancement facility 1` the llvm naming is inconsistent. On the other hand, the cpuinfo names are very cryptic, and aren't found in the IBM documentation.

r? ``@Amanieu``

cc ``@uweigand`` ``@taiki-e``
2025-02-21 12:45:22 +01:00
Ralf Jung
f7ae9e11fc adjust_abi: make fallback logic for ABIs a bit easier to read 2025-02-21 12:21:38 +01:00