Commit Graph

1585 Commits

Author SHA1 Message Date
Antoni Boucher
ae84d258c9 Fix undefined function error 2024-12-13 10:46:31 -05:00
Antoni Boucher
3cb8b1b684 Fix formatting 2024-12-11 14:15:32 -05:00
Antoni Boucher
f563abf1dd Rename UI tests 2024-12-11 14:15:16 -05:00
Antoni Boucher
c55f60805d Fix tests 2024-12-11 14:07:01 -05:00
Antoni Boucher
d6aedffac2 Fix compilation for libgccjit12 2024-12-11 13:53:23 -05:00
Antoni Boucher
526285c4b4 Fix clippy warnings 2024-12-11 13:49:37 -05:00
Antoni Boucher
1ef84a0626 Fix formatting 2024-12-11 13:43:53 -05:00
Antoni Boucher
6b252058e6 Update patch 2024-12-11 13:42:00 -05:00
Antoni Boucher
3dddf72f99 Update nightly version 2024-12-11 13:41:46 -05:00
Antoni Boucher
562aeb4c32 Merge branch 'master' into sync_from_rust_2024_12_11 2024-12-11 13:40:46 -05:00
antoyo
eb87eab292
Merge pull request #577 from rust-lang/fix/lld
Use casts instead of bitcast between pointers and integers to fix issues when using the lld linker
2024-12-11 13:28:13 -05:00
Antoni Boucher
ba97c7f418 Use casts instead of bitcast between pointers and integers to fix issues when using the lld linker 2024-12-11 12:52:27 -05:00
Jack Wrenn
691aec2ef3 Make Copy unsafe to implement for ADTs with unsafe fields
As a rule, the application of `unsafe` to a declaration requires that use-sites
of that declaration also require `unsafe`. For example, a field declared
`unsafe` may only be read in the lexical context of an `unsafe` block.

For nearly all safe traits, the safety obligations of fields are explicitly
discharged when they are mentioned in method definitions. For example,
idiomatically implementing `Clone` (a safe trait) for a type with unsafe fields
will require `unsafe` to clone those fields.

Prior to this commit, `Copy` violated this rule. The trait is marked safe, and
although it has no explicit methods, its implementation permits reads of `Self`.

This commit resolves this by making `Copy` conditionally safe to implement. It
remains safe to implement for ADTs without unsafe fields, but unsafe to
implement for ADTs with unsafe fields.

Tracking: #132922
2024-12-07 20:50:00 +00:00
Ben Kimock
2c205e1d44 Remove polymorphization 2024-12-06 16:42:09 -05:00
Matthias Krüger
714c820e64 Rollup merge of #130777 - azhogin:azhogin/reg-struct-return, r=workingjubilee
rust_for_linux: -Zreg-struct-return commandline flag for X86 (#116973)

Command line flag `-Zreg-struct-return` for X86 (32-bit) for rust-for-linux.
This flag enables the same behavior as the `abi_return_struct_as_int` target spec key.

- Tracking issue: https://github.com/rust-lang/rust/issues/116973
2024-12-06 09:27:38 +01:00
Matthias Krüger
a3a4245341 Rollup merge of #133395 - calebzulawski:simd_relaxed_fma, r=workingjubilee
Add simd_relaxed_fma intrinsic

Adds compiler support for https://github.com/rust-lang/portable-simd/issues/387#issuecomment-2337169786

r? `@workingjubilee`

cc `@RalfJung` is this kind of nondeterminism a problem for miri/opsem?
2024-12-03 07:48:33 +01:00
Andrew Zhogin
3ee22a4131 rust_for_linux: -Zreg-struct-return commandline flag for X86 (#116973) 2024-12-02 01:14:40 +07:00
Taiki Endo
7c8599b6ba Support #[repr(simd)] types in input/output of PowerPC inline assembly 2024-11-29 00:24:36 +09:00
antoyo
9e90bed67d
Merge pull request #573 from rust-lang/update-gcc-2024-11-21
Update for new version of gcc
2024-11-26 17:03:49 -05:00
Antoni Boucher
6142a319ae Update for new version of gcc 2024-11-26 12:32:23 -05:00
Taiki Endo
9e22b5701d Support predicate registers (clobber-only) in Hexagon inline assembly 2024-11-25 23:11:17 +09:00
Taiki Endo
968e79b0ec Make s390x non-clobber-only vector register support unstable 2024-11-24 21:42:22 +09:00
Caleb Zulawski
d6bf793bed Add simd_relaxed_fma intrinsic 2024-11-23 14:39:42 -05:00
Taiki Endo
9cff0b1164 Support input/output in vector registers of s390x inline assembly 2024-11-22 04:18:14 +09:00
Kyle Huey
fcbc3d97b8 When the required discriminator value exceeds LLVM's limits, drop the debug info for the function instead of panicking.
The maximum discriminator value LLVM can currently encode is 2^12. If macro use
results in more than 2^12 calls to the same function attributed to the same
callsite, and those calls are MIR-inlined, we will require more than the maximum
discriminator value to completely represent the debug information. Once we reach
that point drop the debug info instead.
2024-11-19 05:19:09 -08:00
antoyo
ab360ea690
Merge pull request #572 from rust-lang/fix/volatile
Fix volatile loads and stores
2024-11-18 19:22:56 -05:00
Antoni Boucher
b9cb8ebca6 Add missing location info 2024-11-18 18:55:57 -05:00
Antoni Boucher
c2e6d38b8a Remove unnecessary bitcast 2024-11-18 18:47:11 -05:00
Antoni Boucher
337a67de49 Add username to FIXME and TODO 2024-11-18 18:37:45 -05:00
yvt
a583963bd3 Implement volatile store 2024-11-18 17:14:44 -05:00
Antoni Boucher
6a1ecf3ef5 Add read_volatile to volatile test 2024-11-18 17:03:33 -05:00
yvt
f14161ea35 Add a test for volatile loads and stores 2024-11-18 15:30:04 -05:00
lcnr
17410a7ba2 use TypingEnv when no infcx is available
the behavior of the type system not only depends on the current
assumptions, but also the currentnphase of the compiler. This is
mostly necessary as we need to decide whether and how to reveal
opaque types. We track this via the `TypingMode`.
2024-11-18 10:38:56 +01:00
Jiri Bobek
21056f8f2c Likely unlikely fix 2024-11-17 21:49:10 +01:00
Matthias Krüger
415c502d83 Rollup merge of #132702 - 1c3t3a:issue-132615, r=rcvalle
CFI: Append debug location to CFI blocks

Currently we're not appending debug locations to the inserted CFI blocks. This shows up in #132615 and #100783. This change fixes that by passing down the debug location to the CFI type-test generation and appending it to the blocks.

Credits also belong to `@jakos-sec` who worked with me on this.
2024-11-12 23:26:41 +01:00
Bastian Kersting
bed136fb2d CFI: Append debug location to CFI blocks 2024-11-11 09:17:43 +00:00
bjorn3
62c6e498cd Add a default implementation for CodegenBackend::link
As a side effect this should add raw-dylib support to cg_gcc as the
default ArchiveBuilderBuilder that is used implements
create_dll_import_lib. I haven't tested if the raw-dylib support
actually works however.
2024-11-09 20:42:56 +00:00
Ralf Jung
f0368983da remove support for rustc_safe_intrinsic attribute; use rustc_intrinsic functions instead 2024-11-08 09:16:00 +01:00
Jubilee
c0e98dea6a Rollup merge of #130586 - dpaoliello:fixrawdylib, r=wesleywiser
Set "symbol name" in raw-dylib import libraries to the decorated name

`windows-rs` received a bug report that mixing raw-dylib generated and the Windows SDK import libraries was causing linker failures: <https://github.com/microsoft/windows-rs/issues/3285>

The root cause turned out to be #124958, that is we are not including the decorated name in the import library and so the import name type is also not being correctly set.

This change modifies the generation of import libraries to set the "symbol name" to the fully decorated name and correctly marks the import as being data vs function.

Note that this also required some changes to how the symbol is named within Rust: for MSVC we now need to use the decorated name but for MinGW we still need to use partially decorated (or undecorated) name.

Fixes #124958

Passing i686 MSVC and MinGW build: <https://github.com/rust-lang/rust/actions/runs/11000433888?pr=130586>

r? `@ChrisDenton`
2024-11-07 18:48:20 -08:00
Taiki Endo
051b774d2a Basic inline assembly support for SPARC and SPARC64 2024-11-07 21:19:03 +09:00
bors
92c27e8b37 Auto merge of #129884 - RalfJung:forbidden-target-features, r=workingjubilee
mark some target features as 'forbidden' so they cannot be (un)set with -Ctarget-feature

The context for this is https://github.com/rust-lang/rust/issues/116344: some target features change the way floats are passed between functions. Changing those target features is unsound as code compiled for the same target may now use different ABIs.

So this introduces a new concept of "forbidden" target features (on top of the existing "stable " and "unstable" categories), and makes it a hard error to (un)set such a target feature. For now, the x86 and ARM feature `soft-float` is on that list. We'll have to make some effort to collect more relevant features, and similar features from other targets, but that can happen after the basic infrastructure for this landed. (These features are being collected in https://github.com/rust-lang/rust/issues/131799.)

I've made this a warning for now to give people some time to speak up if this would break something.

MCP: https://github.com/rust-lang/compiler-team/issues/780
2024-11-05 16:25:45 +00:00
bors
b664093726 Auto merge of #131341 - taiki-e:ppc-clobber-abi, r=bzEq,workingjubilee
Support clobber_abi and vector registers (clobber-only) in PowerPC inline assembly

This supports `clobber_abi` which is one of the requirements of stabilization mentioned in #93335.

This basically does a similar thing I did in https://github.com/rust-lang/rust/pull/130630 to implement `clobber_abi` for s390x, but for powerpc/powerpc64/powerpc64le.
- This also supports vector registers (as `vreg`) as clobber-only, which need to support clobbering of them to implement `clobber_abi`.
- `vreg` should be able to accept `#[repr(simd)]` types as input/output if the unstable `altivec` target feature is enabled, but `core::arch::{powerpc,powerpc64}` vector types, `#[repr(simd)]`, and `core::simd` are all unstable, so the fact that this is currently a clobber-only should not be considered a blocker of clobber_abi implementation or stabilization. So I have not implemented it in this PR.
  - See https://github.com/rust-lang/rust/pull/131551 (which is based on this PR) for a PR to implement this.
  - (I'm not sticking to whether that PR should be a separate PR or part of this PR, so I can merge that PR into this PR if needed.)

Refs:
- PPC32 SysV: Section "Function Calling Sequence" in [System V Application Binary Interface PowerPC Processor Supplement](https://refspecs.linuxfoundation.org/elf/elfspec_ppc.pdf)
- PPC64 ELFv1: Section 3.2 "Function Calling Sequence" in [64-bit PowerPC ELF Application Binary Interface Supplement](https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#FUNC-CALL)
- PPC64 ELFv2: Section 2.2 "Function Calling Sequence" in [64-Bit ELF V2 ABI Specification](https://openpowerfoundation.org/specifications/64bitelfabi/)
- AIX: [Register usage and conventions](https://www.ibm.com/docs/en/aix/7.3?topic=overview-register-usage-conventions), [Special registers in the PowerPC®](https://www.ibm.com/docs/en/aix/7.3?topic=overview-special-registers-in-powerpc), [AIX vector programming](https://www.ibm.com/docs/en/aix/7.3?topic=concepts-aix-vector-programming)
- Register definition in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/PowerPC/PPCRegisterInfo.td#L189

If I understand the above four ABI documentations correctly, except for the PPC32 SysV's VR (Vector Registers) and 32-bit AIX (currently not supported by rustc)'s r13, there does not appear to be important differences in terms of implementing `clobber_abi`:
- The above four ABIs are consistent about FPR (0-13: volatile, 14-31: nonvolatile), CR (0-1,5-7: volatile, 2-4: nonvolatile), XER (volatile), and CTR (volatile).
- As for GPR, only the registers we are treating as reserved are slightly different
  - r0, r3-r12 are volatile
  - r1(sp, reserved), r14-31 are nonvolatile
  - r2(reserved) is TOC pointer in PPC64 ELF/AIX, system-reserved register in PPC32 SysV (AFAIK used as thread pointer in Linux/BSDs)
  - r13(reserved for non-32-bit-AIX) is thread pointer in PPC64 ELF, small data area pointer register in PPC32 SysV, "reserved under 64-bit environment; not restored across system calls[^r13]" in AIX)
- As for FPSCR, volatile in PPC64 ELFv1/AIX, some fields are volatile only in certain situations (rest are volatile) in PPC32 SysV/PPC64 ELFv2.
- As for VR (Vector Registers), it is not mentioned in PPC32 SysV, v0-v19 are volatile in both in PPC64 ELF/AIX, v20-v31 are nonvolatile in PPC64 ELF, reserved or nonvolatile depending on the ABI ([vec-extabi vs vec-default in LLVM](https://reviews.llvm.org/D89684), we are [using vec-extabi](https://github.com/rust-lang/rust/pull/131341#discussion_r1797693299)) in AIX:
  > When the default Vector enabled mode is used, these registers are reserved and must not be used.
  > In the extended ABI vector enabled mode, these registers are nonvolatile and their values are preserved across function calls

  I left [FIXME comment about PPC32 SysV](https://github.com/rust-lang/rust/pull/131341#discussion_r1790496095) and added ABI check for AIX.
- As for VRSAVE, it is not mentioned in PPC32 SysV, nonvolatile in PPC64 ELFv1, reserved in PPC64 ELFv2/AIX
- As for VSCR, it is not mentioned in PPC32 SysV/PPC64 ELFv1, some fields are volatile only in certain situations (rest are volatile) in PPC64 ELFv2, volatile in AIX

We are currently treating r1-r2, r13 (non-32-bit-AIX), r29-r31, LR, CTR, and VRSAVE as reserved.
We are currently not processing anything about FPSCR and VSCR, but I feel those are things that should be processed by `preserves_flags` rather than `clobber_abi` if we need to do something about them. (However, PPCRegisterInfo.td in LLVM does not seem to define anything about them.)

Replaces #111335 and #124279

cc `@ecnelises` `@bzEq` `@lu-zero`

r? `@Amanieu`

`@rustbot` label +O-PowerPC +A-inline-assembly

[^r13]: callee-saved, according to [LLVM](6a6af0246b/llvm/lib/Target/PowerPC/PPCCallingConv.td (L322)) and [GCC](a9173a50e7/gcc/config/rs6000/rs6000.h (L859)).
2024-11-05 03:13:47 +00:00
Ralf Jung
4843153a0a mark some target features as 'forbidden' so they cannot be (un)set
For now, this is just a warning, but should become a hard error in the future
2024-11-04 22:56:47 +01:00
bjorn3
45437fb8c8 Reduce dependence on the target name
The target name can be anything with custom target specs. Matching on
fields inside the target spec is much more robust than matching on the
target name.
2024-11-03 18:29:01 +00:00
Noratrieb
049c24e164 Rename target triple to target tuple in many places in the compiler
This changes the naming to the new naming, used by `--print
target-tuple`.
It does not change all locations, but many.
2024-11-02 21:29:59 +01:00
Taiki Endo
5213c6f6ba Support clobber_abi and vector registers (clobber-only) in PowerPC inline assembly 2024-11-02 20:26:08 +09:00
Jubilee Young
58110243e9 cg_gcc: rustc_abi::Abi => BackendRepr 2024-10-29 15:01:01 -07:00
Deadbeef
9f20eb7597 Effects cleanup
- removed extra bits from predicates queries that are no longer needed in the new system
- removed the need for `non_erasable_generics` to take in tcx and DefId, removed unused arguments in callers
2024-10-26 10:19:07 +08:00
Zalathar
7f0ca5a8af coverage: SSA doesn't need to know about instrprof_increment 2024-10-25 14:24:05 +11:00
Stuart Cook
9865a6c6e0 Rollup merge of #130225 - adetaylor:rename-old-receiver, r=wesleywiser
Rename Receiver -> LegacyReceiver

As part of the "arbitrary self types v2" project, we are going to replace the current `Receiver` trait with a new mechanism based on a new, different `Receiver` trait.

This PR renames the old trait to get it out the way. Naming is hard. Options considered included:
* HardCodedReceiver (because it should only be used for things in the standard library, and hence is sort-of hard coded)
* LegacyReceiver
* TargetLessReceiver
* OldReceiver

These are all bad names, but fortunately this will be temporary. Assuming the new mechanism proceeds to stabilization as intended, the legacy trait will be removed altogether.

Although we expect this trait to be used only in the standard library, we suspect it may be in use elsehwere, so we're landing this change separately to identify any surprising breakages.

It's known that this trait is used within the Rust for Linux project; a patch is in progress to remove their dependency.

This is a part of the arbitrary self types v2 project,
https://github.com/rust-lang/rfcs/pull/3519
https://github.com/rust-lang/rust/issues/44874

r? `@wesleywiser`
2024-10-24 14:19:53 +11:00