Commit Graph

4562 Commits

Author SHA1 Message Date
bjorn3
9fd3b18b0b Avoid depending on the unadjusted abi
It is ill defined and for this specific case it may become impossible
to call using Cranelift in the future.
2024-12-05 15:36:03 +00:00
bjorn3
0974099e30 Revert "Switch to -ffunction-sections by default"
This reverts commit 65c5c7f8cf.

It unfortunately regresses the size of the target dir by a non-trivial
amount. It could be re-enabled again once each subsection doesn't get a
unique name anymore.
2024-12-05 12:43:01 +00:00
bjorn3
92b5873072 Make artifact_size usage closer to what cg_llvm does 2024-12-05 12:09:07 +00:00
bjorn3
65c5c7f8cf Switch to -ffunction-sections by default
With lld the perf difference is within noise while producing slightly
(or in exceptional cases significantly) smaller binaries.
2024-12-05 12:03:58 +00:00
bjorn3
a767a103bb Extract codegen_cgu_content 2024-12-05 11:41:14 +00:00
bjorn3
53e1043e82 Extract emit_allocator_module 2024-12-05 11:38:18 +00:00
bjorn3
1d940adc86 Extract emit_metadata_module 2024-12-05 11:37:19 +00:00
bjorn3
623a6dadfd Move SelfProfilerRef out of CodegenCx 2024-12-05 11:33:03 +00:00
bjorn3
357deaa849 Move disabling of f16 and f128 in compiler-builtins to liballoc
This way it gets disabled even when trying to compile just liballoc and
not the sysroot crate.
2024-12-04 14:38:37 +00:00
bjorn3
28533886c3 Fix rustc test suite 2024-12-04 12:24:24 +00:00
bjorn3
eff1c5d627 Rustup to rustc 1.85.0-nightly (c44b3d50f 2024-12-03) 2024-12-04 11:25:10 +00:00
bjorn3
812edd21e0 Sync from rust c44b3d50fe 2024-12-04 11:08:01 +00:00
Matthias Krüger
7174bcc8d6 Rollup merge of #133545 - clubby789:symbol-intern-lit, r=jieyouxu
Lint against Symbol::intern on a string literal

Disabled in tests where this doesn't make much sense
2024-12-03 17:27:06 +01:00
Matthias Krüger
c5acac93fd Rollup merge of #133395 - calebzulawski:simd_relaxed_fma, r=workingjubilee
Add simd_relaxed_fma intrinsic

Adds compiler support for https://github.com/rust-lang/portable-simd/issues/387#issuecomment-2337169786

r? `@workingjubilee`

cc `@RalfJung` is this kind of nondeterminism a problem for miri/opsem?
2024-12-03 07:48:33 +01:00
bjorn3
95bb635853 Fix std_example on s390x 2024-11-28 18:26:56 +00:00
bjorn3
e82b533efd Fix rustc test suite 2024-11-28 18:10:15 +00:00
bjorn3
e595d03b1d Rustup to rustc 1.85.0-nightly (6b6a867ae 2024-11-27) 2024-11-28 17:46:12 +00:00
bjorn3
632ccacd81 Sync from rust 6b6a867ae9 2024-11-28 17:36:44 +00:00
clubby789
a2e9aac905 Replace Symbol::intern calls with preinterned symbols 2024-11-28 15:45:27 +00:00
Guillaume Gomez
1aded6079a Rollup merge of #133463 - taiki-e:aarch64-asm-x18, r=Amanieu
Fix handling of x18 in AArch64 inline assembly on ohos/trusty or with -Zfixed-x18

Currently AArch64 inline assembly allows using x18 on ohos/trusty or with -Zfixed-x18.

7db7489f9b/compiler/rustc_target/src/asm/aarch64.rs (L74-L76)

However, x18 is reserved in these environments and should not be allowed in the input/output operands of inline assemblies as it is in Android, Windows, etc..

7db7489f9b/compiler/rustc_target/src/spec/targets/aarch64_unknown_linux_ohos.rs (L19)
7db7489f9b/compiler/rustc_target/src/spec/targets/aarch64_unknown_trusty.rs (L18)
7db7489f9b/compiler/rustc_codegen_llvm/src/llvm_util.rs (L764-L771)

(As for ohos, +reserve-x18 is [redundant](c417b7a695 (diff-0ddf23e0bf2b28b2d05f842f087d1e6f694e8e06d1765e8d0f10d47fddcdff9c)) since 7a966b9188 that starting using llvm's ohos targets. So removed it from target-spec.)

This fix may potentially break the code for tier 2 target (aarch64-unknown-linux-ohos). (As for others, aarch64-unknown-trusty is tier 3 and -Zfixed-x18 is unstable so breaking them should be fine.)
However, in any case, it seems suspicious that the code that is broken by this was sound.

r? `@Amanieu`

`@rustbot` label O-AArch64 +A-inline-assembly
2024-11-28 12:06:02 +01:00
Guillaume Gomez
4161cefabe Rollup merge of #133422 - taiki-e:riscv-e-clobber-abi, r=Amanieu
Fix clobber_abi in RV32E and RV64E inline assembly

Currently clobber_abi in RV32E and RV64E inline assembly is implemented using InlineAsmClobberAbi::RiscV, but broken since x16-x31 cannot be used in RV32E and RV64E.

```
error: cannot use register `x16`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x17`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x28`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x29`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x30`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x31`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^
```

r? `@Amanieu`

`@rustbot` label O-riscv +A-inline-assembly
2024-11-28 12:06:01 +01:00
Taiki Endo
e5bc7e38c3 Fix handling of x18 in AArch64 inline assembly on ohos/trusty or with -Zfixed-x18 2024-11-26 03:10:22 +09:00
Matthias Krüger
e73d32190b Rollup merge of #131664 - taiki-e:s390x-asm-vreg-inout, r=Amanieu
Support input/output in vector registers of s390x inline assembly (under asm_experimental_reg feature)

This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output.

This is unstable and gated under new `#![feature(asm_experimental_reg)]` (tracking issue: https://github.com/rust-lang/rust/issues/133416). If the feature is not enabled, only clober is supported as before.

| Architecture | Register class | Target feature | Allowed types |
| ------------ | -------------- | -------------- | -------------- |
| s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` |

This matches the list of types that are supported by the vector registers in LLVM:
https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313

In addition to `core::simd` types and floats listed above, custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable.

Currently there is no SIMD type for s390x in `core::arch`, but this is tracked in https://github.com/rust-lang/rust/issues/130869.

cc https://github.com/rust-lang/rust/issues/130869 about vector facility support in s390x
cc https://github.com/rust-lang/rust/issues/125398 & https://github.com/rust-lang/rust/issues/116909 about f128 support in asm

`@rustbot` label +O-SystemZ +A-inline-assembly
2024-11-25 07:01:37 +01:00
Taiki Endo
b9e2bdd050 Fix clobber_abi in RV32E and RV64E inline assembly 2024-11-25 00:36:22 +09:00
Taiki Endo
1876e520e8 Make s390x non-clobber-only vector register support unstable 2024-11-24 21:42:22 +09:00
Caleb Zulawski
8f9d76550b Add simd_relaxed_fma intrinsic 2024-11-23 14:39:42 -05:00
lcnr
510943ab55 remove remaining references to Reveal 2024-11-23 13:52:56 +01:00
bjorn3
fdca75c263 Refactor and reduce usage of RelPath 2024-11-21 17:51:18 +00:00
bjorn3
5763c09be1 Remove RelPath::DOWNLOAD 2024-11-21 17:51:14 +00:00
bjorn3
4f213adf09 Inline all RelPath::ensure_fresh 2024-11-21 17:44:01 +00:00
bjorn3
1c372caa33 Make the cold_path intrinsic mark the current block as cold 2024-11-21 14:40:20 +00:00
bjorn3
cb51cfe3d0 Simplify config.rs 2024-11-21 13:06:30 +00:00
bjorn3
5644a0879c Stop passing BackendConfig to run_jit 2024-11-21 13:00:00 +00:00
bjorn3
56a64baa03 Avoid Cell in CodegenCx 2024-11-21 12:49:45 +00:00
bjorn3
5d5cd2a22b Avoid RefCell in CodegenBackend 2024-11-21 12:48:12 +00:00
bjorn3
bd209edb7d Remove disable_incr_cache from BackendConfig 2024-11-21 12:44:54 +00:00
bjorn3
1cc10793f3 Remove enable_verifier from BackendConfig 2024-11-21 12:38:14 +00:00
bjorn3
ebacaee16b Update to Cranelift 0.114 2024-11-21 12:04:27 +00:00
bjorn3
9d1de630fc Fix rustc test suite 2024-11-21 11:42:39 +00:00
bjorn3
a960aac0ba Rustup to rustc 1.84.0-nightly (3fee0f12e 2024-11-20) 2024-11-21 10:31:35 +00:00
bjorn3
d09f798235 Sync from rust 3fee0f12e4 2024-11-21 10:04:31 +00:00
Ding Xiang Fei
329cd79cb4 reduce false positives of tail-expr-drop-order from consumed values
take 2

open up coroutines

tweak the wordings

the lint works up until 2021

We were missing one case, for ADTs, which was
causing `Result` to yield incorrect results.

only include field spans with significant types

deduplicate and eliminate field spans

switch to emit spans to impl Drops

Co-authored-by: Niko Matsakis <nikomat@amazon.com>

collect drops instead of taking liveness diff

apply some suggestions and add explantory notes

small fix on the cache

let the query recurse through coroutine

new suggestion format with extracted variable name

fine-tune the drop span and messages

bugfix on runtime borrows

tweak message wording

filter out ecosystem types earlier

apply suggestions

clippy

check lint level at session level

further restrict applicability of the lint

translate bid into nop for stable mir

detect cycle in type structure
2024-11-20 20:53:11 +08:00
bors
67c8877102 Auto merge of #133212 - lcnr:questionable-uwu, r=compiler-errors
continue `ParamEnv` to `TypingEnv` transition

cc #132279

r? `@compiler-errors`
2024-11-20 06:22:01 +00:00
lcnr
bf45e9f7f3 InterpCx store TypingEnv instead of a ParamEnv 2024-11-19 21:36:23 +01:00
lcnr
a4acd22dbb move fn is_item_raw to TypingEnv 2024-11-19 18:06:20 +01:00
Jieyou Xu
c5c3709d80 Explicitly disable llvm tools for cranelift 2024-11-19 20:29:54 +08:00
bors
43181b4d75 Auto merge of #132460 - lcnr:questionable-uwu, r=compiler-errors
Use `TypingMode` throughout the compiler instead of `ParamEnv`

Hopefully the biggest single PR as part of https://github.com/rust-lang/types-team/issues/128.

## `infcx.typing_env` while defining opaque types

I don't know how'll be able to correctly handle opaque types when using something taking a `TypingEnv` while defining opaque types. To correctly handle the opaques we need to be able to pass in the current `opaque_type_storage` and return constraints, i.e. we need to use a proper canonical query. We should migrate all the queries used during HIR typeck and borrowck where this matters to proper canonical queries. This is

## `layout_of` and `Reveal::All`

We convert the `ParamEnv` to `Reveal::All` right at the start of the `layout_of` query, so I've changed callers of `layout_of` to already use a post analysis `TypingEnv` when encountering it.

ca87b535a0/compiler/rustc_ty_utils/src/layout.rs (L51)

## `Ty::is_[unpin|sized|whatever]`

I haven't migrated `fn is_item_raw` to use `TypingEnv`, will do so in a followup PR, this should significantly reduce the amount of `typing_env.param_env`. At some point there will probably be zero such uses as using the type system while ignoring the `typing_mode` is incorrect.

## `MirPhase` and phase-transitions

When inside of a MIR-body, we can mostly use its `MirPhase` to figure out the right `typing_mode`. This does not work during phase transitions, most notably when transitioning from `Analysis` to `Runtime`:

dae7ac133b/compiler/rustc_mir_transform/src/lib.rs (L606-L625)

All these passes still run with `MirPhase::Analysis`, but we should only use `Reveal::All` once we're run the `RevealAll` pass. This required me to manually construct the right `TypingEnv` in all these passes. Given that it feels somewhat easy to accidentally miss this going forward, I would maybe like to change `Body::phase` to an `Option` and replace it at the start of phase transitions. This then makes it clear that the MIR is currently in a weird state.

r? `@ghost`
2024-11-18 21:07:05 +00:00
lcnr
19a8eb2a7f use TypingEnv when no infcx is available
the behavior of the type system not only depends on the current
assumptions, but also the currentnphase of the compiler. This is
mostly necessary as we need to decide whether and how to reveal
opaque types. We track this via the `TypingMode`.
2024-11-18 10:38:56 +01:00
Ralf Jung
22b0e3c0d4 remove pointless cold_path impl in interpreter 2024-11-18 08:41:28 +01:00
Jiri Bobek
1a27566d20 Likely unlikely fix 2024-11-17 21:49:10 +01:00