eZio Pan
b4399a1bf5
timer-doc-fix
2024-02-10 16:22:36 +08:00
Dario Nieuwenhuis
832776d2c7
stm32: update metapac.
2024-02-10 02:50:35 +01:00
eZio Pan
8fd803a5fe
use cfg_if to reduce macro condition
2024-02-10 00:00:43 +01:00
eZio Pan
0f94006be3
doc fix
2024-02-10 00:00:43 +01:00
eZio Pan
6c690ab259
restore original public API of timer, but keep new PAC
2024-02-10 00:00:43 +01:00
eZio Pan
b3cdf3a040
bug fix
2024-02-10 00:00:43 +01:00
eZio Pan
319f10da5d
stm32-timer: filter out c0, f1 and f37x
2024-02-10 00:00:43 +01:00
eZio Pan
5b646bc3bd
stm32-timer: L0 is special
2024-02-10 00:00:43 +01:00
eZio Pan
d538829f2f
add methods with macro
2024-02-10 00:00:43 +01:00
Dario Nieuwenhuis
53bf0332e9
asdkf
2024-02-10 00:00:43 +01:00
eZio Pan
dc4898ca89
update timer mod after stm32-metapac timer_v2
2024-02-09 23:58:13 +01:00
eZio Pan
d6636ca116
minor fix
2024-02-09 23:57:09 +01:00
Dario Nieuwenhuis
04147b4147
Merge pull request #2544 from shufps/feat/adc-l0
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Feat/adc l0
2024-02-09 22:48:57 +00:00
Ulf Lilleengen
1641f8a27e
Merge pull request #2397 from tyler-gilbert/add-write-immediate-api-dma-ring-buffer
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Add write_immediate() function to STM32 DMA ringbufer API
2024-02-09 20:05:41 +00:00
shufps
34c71b58cf
made adc example working with default clock configuration and switched in v1 to PCLK/2 per default
2024-02-08 11:28:53 +01:00
shufps
dabe48c3bd
fmt
2024-02-08 11:15:28 +01:00
shufps
8d0a9bbefb
clippy
2024-02-08 11:14:14 +01:00
shufps
ab8f25fd78
added support for ADC of L0s
2024-02-08 10:47:26 +01:00
Dario Nieuwenhuis
2c5426aa5c
Merge pull request #2539 from badrbouslikhin/stm32h7-flash-improvements
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fix(stm32h7/flash): enhance resilience to program sequence errors (pgserr)
2024-02-06 15:58:50 +00:00
Badr Bouslikhin
aab5da1d3b
fix(stm32h7/flash): enhance resilience to program sequence errors (pgserr)
2024-02-06 12:30:04 +01:00
Badr Bouslikhin
e72cc9fb24
fix(stm32/h7): use correct unit in vco clock check
2024-02-06 11:33:39 +01:00
Dario Nieuwenhuis
e25eb6ca59
Merge pull request #2529 from GrantM11235/buffered-uart-doc-links
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stm32/usart: Add doc links to buffered uarts
2024-02-04 23:29:27 +01:00
Dario Nieuwenhuis
6c72638ed0
stm32/rcc: fix more build failures.
2024-02-04 22:47:29 +01:00
Dario Nieuwenhuis
e3fe08428f
stm32/rcc: fix build for some f0 and l4 chips.
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Fixes #2531
2024-02-04 22:07:17 +01:00
Grant Miller
87a52f5ead
stm32/usart: Add doc links to buffered uarts
2024-02-03 17:04:20 -06:00
Stefan Gehr
b9d0069671
correct spelling of the word "receive"
2024-02-03 14:56:31 +01:00
Dario Nieuwenhuis
9866847375
stm32: autogenerate clocks struct, enable mux for all chips.
2024-02-02 23:24:34 +01:00
Dario Nieuwenhuis
a099084bff
Merge pull request #2520 from Ecco/stm32wba-rcc-v3
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Migrate STM32WBA to RCCv3
2024-02-02 20:48:39 +00:00
Romain Goyet
92690d8590
Migrate STM32WBA to RCCv3
2024-02-02 14:12:26 -05:00
Dario Nieuwenhuis
e05c8e2f44
stm32/dac: use autogenerated RCC impls.
2024-02-01 23:47:30 +01:00
Dario Nieuwenhuis
e7d1119750
stm32: automatically use refcounting for rcc bits used multiple times.
2024-02-01 23:15:17 +01:00
Joonas Javanainen
7e0f287431
Fix ADC max frequency for F2
2024-02-01 21:58:36 +02:00
Joonas Javanainen
21024e8638
Fix F2 temperature sensor ADC channel
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On all F2 devices (F205/207/215/217) the sensor is connected to
ADC1_IN16, and is not shared with VBAT which is connected to ADC1_IN18.
2024-02-01 21:48:29 +02:00
Romain Goyet
aa767272a8
STM32WBA's high speed external clock has to run at 32 MHz
2024-02-01 13:42:48 -05:00
Dario Nieuwenhuis
7e02389995
Merge pull request #2410 from eZioPan/waveform-on-CHx
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impl waveform with TIM OC Channel DMA
2024-02-01 01:02:01 +00:00
Dario Nieuwenhuis
e613324e16
stm32/eth: rename new_rmii to new, update metapac to fix issues with PC2_C.
2024-02-01 01:39:52 +01:00
Simon B. Gasse
42d8f3930a
Implement MII interface
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- Extend the eth/v2 module to support MII besides RMII.
- Replace `Ethernet::new` with `Ethernet::new_mii` and
`Ethernet::new_rmii`.
- Update ethernet examples.
- Add example for MII ethernet.
2024-02-01 01:33:34 +01:00
Corey Schuhen
1de78d0490
Initial FDCAN driver implementation.
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Original author:
Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Cleanup and documentaion by:
Tomasz bla Fortuna <bla@reactor.local>
Corey Schuhen <cschuhen@gmail.com>
Use new PAC method now that the names are common.
Use broken out definitions that can be shared with bxcan
Populate Rx struct with an embassy timestamp.
Remove use of RefCell.
As per review comment. - THis will probably get squashed down.
Fix
2024-01-31 05:40:05 +10:00
Tomasz bla Fortuna
03ba45065e
Add FDCAN clock registers to G4 RCC.
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Author: Adam Morgan <adam@luci.com>
Break definitions out of bxcan that can be used innm fdcan.
Typo
2024-01-31 05:40:05 +10:00
Tomasz bla Fortuna
a91a7a8557
Add FDCAN dependency in correct flavor based on selected chip.
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Author: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Change from review.
2024-01-31 05:40:05 +10:00
Dario Nieuwenhuis
5b2293e2b1
update stm32-metapac.
2024-01-30 02:34:12 +01:00
Dario Nieuwenhuis
3387ee7238
stm32/gpio: remove generics.
2024-01-22 21:31:06 +01:00
Dario Nieuwenhuis
43b6258a69
Merge pull request #2416 from andresv/stm32-fix-buffered-uart-flush
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stm32: fix buffered uart flush
2024-01-20 01:50:55 +00:00
Dario Nieuwenhuis
67159d80bb
Merge pull request #2429 from jr-oss/stm32_simple_pwm_add_set_output_compare_mode
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stm32/simple_pwm: add set_output_compare_mode
2024-01-20 01:33:49 +00:00
Dario Nieuwenhuis
326bff322e
Merge pull request #2415 from hdoordt/patch-1
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Make adc::Resolution::to_max_count const
2024-01-20 01:31:22 +00:00
Andres Vahter
ec2e3de0f4
stm32 uart: fix buffered flush for usart_v1, usart_v2
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There is one caveat. For some reason with first send using usart_v1/usart_v2 TC flag appears right after first byte from buffer is written to DR. Consecutive transfers work as expected - TC flag appears when last byte is fully transferred to wire.
2024-01-20 00:15:40 +01:00
Andres Vahter
534c53c901
stm32 uart: remove unwrap
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unwraps take more space because of panics
2024-01-20 00:15:40 +01:00
Andres Vahter
c936d66934
stm32 uart: fix flush for non usart_v4 variants
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Byte was written to TDR and right after that waker was called. This means `flush` would see that `tx_buf` is empty and can return Ready although actually hardware was still writing this last byte to the wire.
With this change non `usart_v4 ` variants would also use TC interrupt to check when last byte was sent out.
2024-01-20 00:15:39 +01:00
Andres Vahter
17d6e4eefe
stm32 uart: do not wake after sending each byte
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usart_v4 uses TC interrupt to see if all bytes are sent out from the FIFO and waker is called from this interrupt. This minimises unnecessary wakeups during sending.
2024-01-20 00:15:39 +01:00
Andres Vahter
ec47e931ac
stm32: fix buffered uart flush
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usart_v4 uses internal FIFO and therefore actually all bytes are not yet sent out although state.tx_buf.is_empty()
2024-01-20 00:15:39 +01:00
