David Haig
32019ed9b7
Allow cmd buffer to be passed in for dma memory
2024-07-17 17:12:37 +01:00
rafael
d9ea5cb015
stm after cargo fix
2024-07-14 17:56:56 +02:00
rafael
c7f775dc20
stm
2024-07-14 16:42:54 +02:00
Ulf Lilleengen
e2f9a48457
Merge pull request #3148 from andresv/stm32-adc-blocking_read
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stm32 adc: introduce blocking_read
2024-07-03 12:45:58 +00:00
Andres Vahter
f851081e09
stm32 adc: introduce blocking_read
2024-07-03 15:20:31 +03:00
Dario Nieuwenhuis
ac5b7edb05
Merge pull request #3144 from Stupremee/better-clock-messages
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Better panic message when peripheral clock is not enabled
2024-07-03 09:30:24 +00:00
Ulf Lilleengen
914d7c7919
Merge pull request #3128 from andresv/stm32-adc-dma-v3
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STM32 ADC v3 and V4 DMA support
2024-07-03 08:13:26 +00:00
Ulf Lilleengen
ef78e3283b
Merge pull request #3143 from andresv/stm32-ringbuffered-adc-docs
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stm32 ringbuffered adc docs
2024-07-03 07:33:10 +00:00
Ulf Lilleengen
b6f76b5ab2
Merge pull request #3110 from liarokapisv/adc_v4_averaging
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stm32 - Adc v4 - Add averaging support.
2024-07-03 07:22:34 +00:00
Ulf Lilleengen
3e70601fc7
Merge pull request #3124 from Adancurusul/dev
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Add adc oversampling support
2024-07-03 07:22:03 +00:00
Justus K
9e4e536769
Better panic message when peripheral clock is not enabled
2024-07-03 08:32:00 +02:00
Ulf Lilleengen
5223923bd2
Merge pull request #3111 from Eekle/feature/async_tsc
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Add async API to TSC
2024-07-02 18:51:50 +00:00
Eekle
d3f8905e93
Use crate level PeriMode
2024-07-02 20:46:05 +02:00
Andres Vahter
d4ff7616f9
stm32 ringbuffered adc docs improvements
2024-07-02 17:35:15 +03:00
Andres Vahter
a4e62314af
stm32: adc v3: fix for newest pac
2024-07-02 17:15:22 +03:00
Andres Vahter
c120efad5b
stm32 adc read_async: add asserts for buf len
2024-07-02 17:07:18 +03:00
Andres Vahter
5e2fd8623a
stm32 adc v3 read_async
2024-07-02 17:07:18 +03:00
Alexandros Liarokapis
02b096915f
add asynchrous sequence read support to adc v4
2024-07-02 17:07:18 +03:00
Andres Vahter
dd69efe708
stm32 ringbuffered adc: add buf size assert
2024-07-02 16:56:19 +03:00
Andres Vahter
b88e1a5d71
stm32 ringbuffered adc docs
2024-07-02 16:53:49 +03:00
Andres Vahter
1f30ad595b
stm32 ringbuffered adc: fix for metapac changes
2024-07-02 09:21:27 +03:00
Andres Vahter
8cbb64226b
update stm32-metapac
2024-07-02 09:15:01 +03:00
Dario Nieuwenhuis
6f21d5e478
Merge pull request #3116 from sethkrie/adc-v2-ringbuf
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ring buffered adc v2
2024-07-02 01:05:49 +00:00
Dario Nieuwenhuis
d6e4086a15
Merge pull request #3089 from qwerty19106/stm32_uart_half_fix_sequential_read_write
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WIP: STM32 Half-Duplex: fix sequential reads and writes
2024-07-02 00:58:54 +00:00
Dario Nieuwenhuis
c0cd851fb9
Merge pull request #3093 from liarokapisv/circular_half_transfer_ir
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Enables half transfer ir when constructing a ReadableDmaRingBuffer
2024-07-02 00:51:05 +00:00
Роман Кривенков
a862334dae
STM32 Half-Duplex: fix sequential reads and writes
2024-07-02 02:45:06 +02:00
Dario Nieuwenhuis
976e9f7fba
Merge pull request #3104 from birdistheword96/main
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Fix: Ensure I2C bus is free before master-write operation
2024-07-01 23:18:55 +00:00
Dario Nieuwenhuis
00babd2ec4
Merge pull request #3126 from ninjasource/stm32-ltdc
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Add support for the stm32 LTDC display peripheral
2024-07-01 23:18:15 +00:00
seth
27652798c7
fix typo, add spaces after //
2024-07-01 06:44:47 -07:00
Eekle
1d1fc9afea
Add async and blocking variants
2024-06-30 11:03:29 +02:00
David Flemström
662e97f7b5
Panic on index-out-of-bounds when releasing RCC node
2024-06-29 01:37:35 +02:00
David Flemström
114dda2fd1
Avoid accidental copy of static var before creating mut ref
2024-06-29 01:34:07 +02:00
David Flemström
2f750a82bf
Swat some other occurrences of .unwrap() that pull in panicing infra
2024-06-28 22:52:21 +02:00
David Flemström
73d937dc33
Remove implicit bounds checking from rcc module
2024-06-28 22:52:10 +02:00
David Haig
6edf7b4688
Applied formatting
2024-06-28 18:17:17 +01:00
David Haig
79f00e54cc
Moved ltdc example to its own crate
2024-06-28 18:11:34 +01:00
David Haig
1123e3fd41
Get dsi_bsp example to compile again
2024-06-28 15:12:17 +01:00
David Haig
47c7bb2bb5
Updated metapac dependency to latest for LTDC support
2024-06-28 11:35:38 +01:00
David Haig
0e84bd8a91
Add support for the stm32 ltdc display peripheral
2024-06-27 20:13:20 +01:00
Chen Yuheng
a0799bf270
Add adc oversampling support
2024-06-27 17:04:26 +08:00
seth
7056783fa2
second adc added to example + API todos completed
2024-06-24 17:53:59 -07:00
seth
f64dd8228b
new PR, taking Dirbao's advice to make the DMA impl in a separate struct that consumes Adc<T> to make RingBufferedAdc<T>. Handling overrun similar to RingBufferedUart
2024-06-24 17:09:43 -07:00
Eekle
7eb605d116
fmt
2024-06-23 16:55:36 +02:00
Eekle
2655426cd8
Add async wait to TSC
2024-06-23 16:43:12 +02:00
Alexandros Liarokapis
3883a5b2de
Enables adc v4 averaging support.
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The Adc v4 peripheral includes a hardware oversampler.
This PR adds an averaging interface that keeps most of the current
interface backwards compatible while allowing for the common use-case
of hardware-averaging. A more comprehensive oversampler interface may
be exposed in the future.
2024-06-23 12:43:24 +03:00
Alexandros Liarokapis
00ff1409cd
Enables half transfer ir when constructing a ReadableDmaRingBuffer
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The half transfer irq needs to be enabled in order for the hardware to
notify the waker when the transfer is at half. This is needed to ensure
no overuns occur when using `ReadableDmaRingBuffer`'s `read_exact`.
Otherwise we are only notified when the DMA has completed its cycle and
is on its way to start overwriting the data. The docs in the dma_bdma
buf module also seem to imply that the half transfer irq must be enabled for
proper operation. The only consumers of the `ReadableDmaRingBuffer` api
are the sai module and the `RingBufferedUartRx`. The former enables the
irq manually when constructing the transfer options while the
latter does not. This may also be the cause for #1441 .
2024-06-23 11:43:50 +03:00
Jamie Bird
18ba56534b
Fix Formatting Issues
2024-06-21 15:29:02 +01:00
Jamie Bird
060d1f6e6f
Fix: Ensure I2C bus is free before master-write operation
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The I2C master-write function was failing when executed immediately after an I2C read operation, requiring manual delays to function correctly. This fix introduces a check to ensure the I2C bus is free before initiating the write operation.
According to the RM0399 manual for STM32H7 chips, the BUSY bit (Bit 15 in the I2C ISR register) indicates whether a communication is in progress on the bus. The BUSY bit is set by hardware when a START condition is detected and cleared when a STOP condition is detected or when PE = 0.
This fix prevents the write operation from starting until the BUSY bit is cleared.
2024-06-21 15:09:57 +01:00
ROMemories
4b0615957f
docs(gpio): fix a typo regarding GPIO speed
2024-06-20 12:09:30 +00:00
Fan Jiang
478cbc6a41
Update Cargo.toml to latest stm32-metapac
2024-06-17 14:09:53 -04:00
