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Fix: Ensure I2C bus is free before master-write operation

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The I2C master-write function was failing when executed immediately after an I2C read operation, requiring manual delays to function correctly. This fix introduces a check to ensure the I2C bus is free before initiating the write operation.

According to the RM0399 manual for STM32H7 chips, the BUSY bit (Bit 15 in the I2C ISR register) indicates whether a communication is in progress on the bus. The BUSY bit is set by hardware when a START condition is detected and cleared when a STOP condition is detected or when PE = 0.

This fix prevents the write operation from starting until the BUSY bit is cleared.
This commit is contained in:
Jamie Bird 2024-06-21 15:09:57 +01:00
parent d5badb94d2
commit 060d1f6e6f
1 changed files with 5 additions and 0 deletions
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embassy-stm32/src/i2c/v2.rs
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@ -109,6 +109,11 @@ impl<'d, M: Mode> I2c<'d, M> {
timeout.check()?;
}
// Wait for the bus to be free
while info.regs.isr().read().busy(){
timeout.check()?;
};
let reload = if reload {
i2c::vals::Reload::NOTCOMPLETED
} else {