The Adc v4 peripheral includes a hardware oversampler.
This PR adds an averaging interface that keeps most of the current
interface backwards compatible while allowing for the common use-case
of hardware-averaging. A more comprehensive oversampler interface may
be exposed in the future.
The half transfer irq needs to be enabled in order for the hardware to
notify the waker when the transfer is at half. This is needed to ensure
no overuns occur when using `ReadableDmaRingBuffer`'s `read_exact`.
Otherwise we are only notified when the DMA has completed its cycle and
is on its way to start overwriting the data. The docs in the dma_bdma
buf module also seem to imply that the half transfer irq must be enabled for
proper operation. The only consumers of the `ReadableDmaRingBuffer` api
are the sai module and the `RingBufferedUartRx`. The former enables the
irq manually when constructing the transfer options while the
latter does not. This may also be the cause for #1441.
The I2C master-write function was failing when executed immediately after an I2C read operation, requiring manual delays to function correctly. This fix introduces a check to ensure the I2C bus is free before initiating the write operation.
According to the RM0399 manual for STM32H7 chips, the BUSY bit (Bit 15 in the I2C ISR register) indicates whether a communication is in progress on the bus. The BUSY bit is set by hardware when a START condition is detected and cleared when a STOP condition is detected or when PE = 0.
This fix prevents the write operation from starting until the BUSY bit is cleared.
This makes location info in defmt logs point to the code calling the macro,
instead of always to fmt.rs as before. Fix works with nightlies
starting with today's, and stable 1.81+.
