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nrf, rp: update set_config
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5ad34404af
commit
d2a2734752
@ -176,7 +176,7 @@ impl<'d, T: Instance> Spim<'d, T> {
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let mut spim = Self { _p: spim };
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let mut spim = Self { _p: spim };
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// Apply runtime peripheral configuration
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// Apply runtime peripheral configuration
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Self::set_config(&mut spim, &config);
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Self::set_config(&mut spim, &config).unwrap();
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// Disable all events interrupts
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -566,7 +566,8 @@ mod eha {
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impl<'d, T: Instance> SetConfig for Spim<'d, T> {
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impl<'d, T: Instance> SetConfig for Spim<'d, T> {
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type Config = Config;
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type Config = Config;
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fn set_config(&mut self, config: &Self::Config) {
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type ConfigError = ();
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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let r = T::regs();
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let r = T::regs();
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// Configure mode.
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// Configure mode.
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let mode = config.mode;
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let mode = config.mode;
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@ -604,5 +605,7 @@ impl<'d, T: Instance> SetConfig for Spim<'d, T> {
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// Set over-read character
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// Set over-read character
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let orc = config.orc;
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let orc = config.orc;
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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Ok(())
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}
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}
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}
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}
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@ -172,7 +172,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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let mut spis = Self { _p: spis };
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let mut spis = Self { _p: spis };
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// Apply runtime peripheral configuration
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// Apply runtime peripheral configuration
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Self::set_config(&mut spis, &config);
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Self::set_config(&mut spis, &config).unwrap();
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// Disable all events interrupts.
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// Disable all events interrupts.
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -467,7 +467,8 @@ macro_rules! impl_spis {
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impl<'d, T: Instance> SetConfig for Spis<'d, T> {
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impl<'d, T: Instance> SetConfig for Spis<'d, T> {
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type Config = Config;
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type Config = Config;
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fn set_config(&mut self, config: &Self::Config) {
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type ConfigError = ();
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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let r = T::regs();
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let r = T::regs();
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// Configure mode.
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// Configure mode.
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let mode = config.mode;
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let mode = config.mode;
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@ -509,5 +510,7 @@ impl<'d, T: Instance> SetConfig for Spis<'d, T> {
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// Configure auto-acquire on 'transfer end' event.
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// Configure auto-acquire on 'transfer end' event.
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let auto_acquire = config.auto_acquire;
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let auto_acquire = config.auto_acquire;
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r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
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r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
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Ok(())
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}
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}
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}
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}
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@ -170,7 +170,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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let mut twim = Self { _p: twim };
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let mut twim = Self { _p: twim };
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// Apply runtime peripheral configuration
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// Apply runtime peripheral configuration
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Self::set_config(&mut twim, &config);
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Self::set_config(&mut twim, &config).unwrap();
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// Disable all events interrupts
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -890,9 +890,12 @@ mod eha {
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impl<'d, T: Instance> SetConfig for Twim<'d, T> {
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impl<'d, T: Instance> SetConfig for Twim<'d, T> {
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type Config = Config;
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type Config = Config;
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fn set_config(&mut self, config: &Self::Config) {
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type ConfigError = ();
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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let r = T::regs();
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let r = T::regs();
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r.frequency
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r.frequency
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.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
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.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
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Ok(())
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}
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}
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}
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}
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@ -597,7 +597,8 @@ mod eha {
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impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
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impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
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type Config = Config;
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type Config = Config;
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fn set_config(&mut self, config: &Self::Config) {
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type ConfigError = ();
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fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
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let p = self.inner.regs();
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let p = self.inner.regs();
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let (presc, postdiv) = calc_prescs(config.frequency);
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let (presc, postdiv) = calc_prescs(config.frequency);
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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@ -607,5 +608,7 @@ impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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w.set_scr(postdiv);
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});
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});
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Ok(())
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}
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}
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}
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}
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