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Update f013.rs

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Eli Orona 2024-02-16 16:47:38 -08:00 committed by GitHub
parent 7592e8be6e
commit c99c4a01a9
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1 changed files with 5 additions and 5 deletions
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embassy-stm32/src/rcc/f013.rs
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@ -87,7 +87,7 @@ pub struct TimClockSources {
pub tim1: TimClockSource, pub tim1: TimClockSource,
#[cfg(any( #[cfg(any(
all(stm32f303, any(package_D, package_E)), all(stm32f303, any(package_D, package_E)),
all(stm32f302, any(package_D, package_E)) all(stm32f302, any(package_D, package_E)),
stm32f398 stm32f398
))] ))]
pub tim2: TimClockSource, pub tim2: TimClockSource,
@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim15 { match config.tim.tim15 {
TimClockSource::PClk2 => {}, TimClockSource::PClk2 => {}
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim16 { match config.tim.tim16 {
TimClockSource::PClk2 => {}, TimClockSource::PClk2 => {}
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim17 { match config.tim.tim17 {
TimClockSource::PClk2 => {}, TimClockSource::PClk2 => {}
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(all(stm32f303, any(package_D, package_E))))] #[cfg(any(all(stm32f303, any(package_D, package_E))))]
match config.tim.tim20 { match config.tim.tim20 {
TimClockSource::PClk2 => {}, TimClockSource::PClk2 => {}
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));