nordic-dev.net/embassy
2
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2024-11-25 08:12:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

nrf: fix wrong order configuring gpios.

Browse Source 
Docs say "PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled."
For some reason nrf52 doesn't care but nrf91 does.
This commit is contained in:
Dario Nieuwenhuis 2024-06-17 22:50:13 +02:00
parent e4c4036a46
commit c48547b475
2 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
embassy-nrf/src/buffered_uarte.rs
View File

@ -304,6 +304,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer); let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer); let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
U::regs().enable.write(|w| w.enable().enabled());
U::Interrupt::pend(); U::Interrupt::pend();
unsafe { U::Interrupt::enable() }; unsafe { U::Interrupt::enable() };
@ -405,6 +406,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
let this = Self::new_innerer(peri, txd, cts, tx_buffer); let this = Self::new_innerer(peri, txd, cts, tx_buffer);
U::regs().enable.write(|w| w.enable().enabled());
U::Interrupt::pend(); U::Interrupt::pend();
unsafe { U::Interrupt::enable() }; unsafe { U::Interrupt::enable() };
@ -602,6 +604,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer); let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
U::regs().enable.write(|w| w.enable().enabled());
U::Interrupt::pend(); U::Interrupt::pend();
unsafe { U::Interrupt::enable() }; unsafe { U::Interrupt::enable() };

5
embassy-nrf/src/uarte.rs
View File

@ -221,6 +221,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
T::Interrupt::unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::enable() }; unsafe { T::Interrupt::enable() };
r.enable.write(|w| w.enable().enabled());
let s = T::state(); let s = T::state();
s.tx_rx_refcount.store(2, Ordering::Relaxed); s.tx_rx_refcount.store(2, Ordering::Relaxed);
@ -319,9 +320,7 @@ pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control
r.psel.cts.write(|w| w.connect().disconnected()); r.psel.cts.write(|w| w.connect().disconnected());
r.psel.rts.write(|w| w.connect().disconnected()); r.psel.rts.write(|w| w.connect().disconnected());
// Enable
apply_workaround_for_enable_anomaly(r); apply_workaround_for_enable_anomaly(r);
r.enable.write(|w| w.enable().enabled());
} }
impl<'d, T: Instance> UarteTx<'d, T> { impl<'d, T: Instance> UarteTx<'d, T> {
@ -369,6 +368,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
T::Interrupt::unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::enable() }; unsafe { T::Interrupt::enable() };
r.enable.write(|w| w.enable().enabled());
let s = T::state(); let s = T::state();
s.tx_rx_refcount.store(1, Ordering::Relaxed); s.tx_rx_refcount.store(1, Ordering::Relaxed);
@ -567,6 +567,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
T::Interrupt::unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::enable() }; unsafe { T::Interrupt::enable() };
r.enable.write(|w| w.enable().enabled());
let s = T::state(); let s = T::state();
s.tx_rx_refcount.store(1, Ordering::Relaxed); s.tx_rx_refcount.store(1, Ordering::Relaxed);