From c48547b475eb039a9d30f4c1e03d0c9f65cdec18 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 17 Jun 2024 22:50:13 +0200
Subject: [PATCH] nrf: fix wrong order configuring gpios.

Docs say "PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled."
For some reason nrf52 doesn't care but nrf91 does.
---
 embassy-nrf/src/buffered_uarte.rs | 3 +++
 embassy-nrf/src/uarte.rs          | 5 +++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 385d4015e..071c18760 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -304,6 +304,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
         let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
 
+        U::regs().enable.write(|w| w.enable().enabled());
         U::Interrupt::pend();
         unsafe { U::Interrupt::enable() };
 
@@ -405,6 +406,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
 
         let this = Self::new_innerer(peri, txd, cts, tx_buffer);
 
+        U::regs().enable.write(|w| w.enable().enabled());
         U::Interrupt::pend();
         unsafe { U::Interrupt::enable() };
 
@@ -602,6 +604,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
 
         let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
 
+        U::regs().enable.write(|w| w.enable().enabled());
         U::Interrupt::pend();
         unsafe { U::Interrupt::enable() };
 
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index fa0a773a8..4cf193617 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -221,6 +221,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
+        r.enable.write(|w| w.enable().enabled());
 
         let s = T::state();
         s.tx_rx_refcount.store(2, Ordering::Relaxed);
@@ -319,9 +320,7 @@ pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control
     r.psel.cts.write(|w| w.connect().disconnected());
     r.psel.rts.write(|w| w.connect().disconnected());
 
-    // Enable
     apply_workaround_for_enable_anomaly(r);
-    r.enable.write(|w| w.enable().enabled());
 }
 
 impl<'d, T: Instance> UarteTx<'d, T> {
@@ -369,6 +368,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
+        r.enable.write(|w| w.enable().enabled());
 
         let s = T::state();
         s.tx_rx_refcount.store(1, Ordering::Relaxed);
@@ -567,6 +567,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
+        r.enable.write(|w| w.enable().enabled());
 
         let s = T::state();
         s.tx_rx_refcount.store(1, Ordering::Relaxed);