mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-21 22:32:29 +00:00
Improve rp2040 i2c slave
This commit takes the fixes and error reporting improvements from jcdickinson's work and applies them without overlaying a software state machine on top of the hardware state machine. Also allows configuration of response to 'general call' writes.
This commit is contained in:
parent
5220453d85
commit
bd0b450ca4
@ -4,6 +4,7 @@ use core::marker::PhantomData;
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use core::task::Poll;
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use core::task::Poll;
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use embassy_hal_internal::into_ref;
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use embassy_hal_internal::into_ref;
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use embassy_time::{block_for, Duration};
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use pac::i2c;
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use pac::i2c;
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use crate::i2c::{
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use crate::i2c::{
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@ -21,6 +22,16 @@ pub enum Error {
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Abort(AbortReason),
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Abort(AbortReason),
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/// User passed in a response buffer that was 0 length
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/// User passed in a response buffer that was 0 length
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InvalidResponseBufferLength,
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InvalidResponseBufferLength,
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/// The response buffer length was too short to contain the message
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///
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/// The length parameter will always be the length of the buffer, and is
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/// provided as a convenience for matching alongside `Command::Write`.
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PartialWrite(usize),
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/// The response buffer length was too short to contain the message
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///
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/// The length parameter will always be the length of the buffer, and is
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/// provided as a convenience for matching alongside `Command::GeneralCall`.
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PartialGeneralCall(usize),
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}
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}
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/// Received command
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/// Received command
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@ -56,17 +67,23 @@ pub enum ReadStatus {
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pub struct Config {
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pub struct Config {
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/// Target Address
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/// Target Address
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pub addr: u16,
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pub addr: u16,
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/// Control if the peripheral should ack to and report general calls.
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pub general_call: bool,
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}
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}
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impl Default for Config {
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impl Default for Config {
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fn default() -> Self {
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fn default() -> Self {
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Self { addr: 0x55 }
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Self {
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addr: 0x55,
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general_call: true,
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}
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}
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}
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}
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}
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/// I2CSlave driver.
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/// I2CSlave driver.
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pub struct I2cSlave<'d, T: Instance> {
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pub struct I2cSlave<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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phantom: PhantomData<&'d mut T>,
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pending_byte: Option<u8>,
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}
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}
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impl<'d, T: Instance> I2cSlave<'d, T> {
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impl<'d, T: Instance> I2cSlave<'d, T> {
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@ -96,7 +113,19 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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w.set_master_mode(false);
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w.set_master_mode(false);
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w.set_ic_slave_disable(false);
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w.set_ic_slave_disable(false);
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w.set_tx_empty_ctrl(true);
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w.set_tx_empty_ctrl(true);
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w.set_rx_fifo_full_hld_ctrl(true);
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// This typically makes no sense for a slave, but it is used to
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// tune spike suppression, according to the datasheet.
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w.set_speed(pac::i2c::vals::Speed::FAST);
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// Generate stop interrupts for general calls
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// This also causes stop interrupts for other devices on the bus but those will not be
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// propagated up to the application.
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w.set_stop_det_ifaddressed(!config.general_call);
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});
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});
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p.ic_ack_general_call()
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.write(|w| w.set_ack_gen_call(config.general_call));
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0. Rx watermark should never change, but Tx watermark will be
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// by a register value of 0. Rx watermark should never change, but Tx watermark will be
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@ -119,7 +148,10 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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T::Interrupt::unpend();
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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unsafe { T::Interrupt::enable() };
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Self { phantom: PhantomData }
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Self {
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phantom: PhantomData,
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pending_byte: None,
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}
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}
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}
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/// Calls `f` to check if we are ready or not.
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/// Calls `f` to check if we are ready or not.
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@ -133,8 +165,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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future::poll_fn(|cx| {
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future::poll_fn(|cx| {
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let r = f(self);
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let r = f(self);
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trace!("intr p: {:013b}", T::regs().ic_raw_intr_stat().read().0);
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if r.is_pending() {
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if r.is_pending() {
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T::waker().register(cx.waker());
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T::waker().register(cx.waker());
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g(self);
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g(self);
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@ -146,14 +176,36 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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}
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}
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#[inline(always)]
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#[inline(always)]
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fn drain_fifo(&mut self, buffer: &mut [u8], offset: usize) -> usize {
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fn drain_fifo(&mut self, buffer: &mut [u8], offset: &mut usize) {
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let p = T::regs();
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let p = T::regs();
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let len = p.ic_rxflr().read().rxflr() as usize;
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let end = offset + len;
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for b in &mut buffer[*offset..] {
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for i in offset..end {
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if let Some(pending) = self.pending_byte.take() {
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buffer[i] = p.ic_data_cmd().read().dat();
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*b = pending;
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*offset += 1;
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continue;
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}
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let status = p.ic_status().read();
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if !status.rfne() {
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break;
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}
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let dat = p.ic_data_cmd().read();
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if *offset != 0 && dat.first_data_byte() {
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// The RP2040 state machine will keep placing bytes into the
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// FIFO, even if they are part of a subsequent write transaction.
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//
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// Unfortunately merely reading ic_data_cmd will consume that
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// byte, the first byte of the next transaction, so we need
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// to store it elsewhere
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self.pending_byte = Some(dat.dat());
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break;
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}
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*b = dat.dat();
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*offset += 1;
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}
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}
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end
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}
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}
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#[inline(always)]
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#[inline(always)]
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@ -165,52 +217,62 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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}
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}
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/// Wait asynchronously for commands from an I2C master.
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/// Wait asynchronously for commands from an I2C master.
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/// `buffer` is provided in case master does a 'write' and is unused for 'read'.
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/// `buffer` is provided in case master does a 'write', 'write read', or 'general call' and is unused for 'read'.
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pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
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pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
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let p = T::regs();
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let p = T::regs();
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p.ic_clr_intr().read();
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// set rx fifo watermark to 1 byte
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// set rx fifo watermark to 1 byte
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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let mut len = 0;
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let mut len = 0;
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let ret = self
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self.wait_on(
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.wait_on(
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|me| {
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|me| {
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let stat = p.ic_raw_intr_stat().read();
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let stat = p.ic_raw_intr_stat().read();
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if p.ic_rxflr().read().rxflr() > 0 {
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len = me.drain_fifo(buffer, len);
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// we're recieving data, set rx fifo watermark to 12 bytes to reduce interrupt noise
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p.ic_rx_tl().write(|w| w.set_rx_tl(11));
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}
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if stat.restart_det() && stat.rd_req() {
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if p.ic_rxflr().read().rxflr() > 0 {
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Poll::Ready(Ok(Command::WriteRead(len)))
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me.drain_fifo(buffer, &mut len);
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} else if stat.gen_call() && stat.stop_det() && len > 0 {
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// we're recieving data, set rx fifo watermark to 12 bytes (3/4 full) to reduce interrupt noise
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Poll::Ready(Ok(Command::GeneralCall(len)))
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p.ic_rx_tl().write(|w| w.set_rx_tl(11));
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} else if stat.stop_det() {
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}
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Poll::Ready(Ok(Command::Write(len)))
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} else if stat.rd_req() {
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if buffer.len() == len {
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Poll::Ready(Ok(Command::Read))
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if stat.gen_call() {
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return Poll::Ready(Err(Error::PartialGeneralCall(buffer.len())));
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} else {
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} else {
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Poll::Pending
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return Poll::Ready(Err(Error::PartialWrite(buffer.len())));
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}
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}
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},
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}
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_restart_det(true);
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w.set_m_gen_call(true);
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w.set_m_rd_req(true);
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w.set_m_rx_full(true);
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});
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},
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)
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.await;
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p.ic_clr_intr().read();
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if stat.restart_det() && stat.rd_req() {
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p.ic_clr_restart_det().read();
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ret
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Poll::Ready(Ok(Command::WriteRead(len)))
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} else if stat.gen_call() && stat.stop_det() && len > 0 {
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p.ic_clr_gen_call().read();
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p.ic_clr_stop_det().read();
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Poll::Ready(Ok(Command::GeneralCall(len)))
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} else if stat.stop_det() && len > 0 {
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p.ic_clr_stop_det().read();
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Poll::Ready(Ok(Command::Write(len)))
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} else if stat.rd_req() {
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p.ic_clr_stop_det().read();
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p.ic_clr_restart_det().read();
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p.ic_clr_gen_call().read();
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Poll::Ready(Ok(Command::Read))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_restart_det(true);
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w.set_m_gen_call(true);
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w.set_m_rd_req(true);
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w.set_m_rx_full(true);
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});
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},
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)
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.await
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}
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}
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/// Respond to an I2C master READ command, asynchronously.
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/// Respond to an I2C master READ command, asynchronously.
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@ -223,47 +285,47 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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let mut chunks = buffer.chunks(FIFO_SIZE as usize);
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let mut chunks = buffer.chunks(FIFO_SIZE as usize);
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let ret = self
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self.wait_on(
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.wait_on(
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|me| {
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|me| {
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if let Err(abort_reason) = me.read_and_clear_abort_reason() {
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if let Err(abort_reason) = me.read_and_clear_abort_reason() {
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if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
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if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
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p.ic_clr_intr().read();
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return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
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return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
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} else {
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return Poll::Ready(Err(abort_reason));
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}
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}
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if let Some(chunk) = chunks.next() {
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me.write_to_fifo(chunk);
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Poll::Pending
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} else {
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} else {
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let stat = p.ic_raw_intr_stat().read();
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return Poll::Ready(Err(abort_reason));
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if stat.rx_done() && stat.stop_det() {
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Poll::Ready(Ok(ReadStatus::Done))
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} else if stat.rd_req() {
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Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
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} else {
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Poll::Pending
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}
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}
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}
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},
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}
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_rx_done(true);
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w.set_m_tx_empty(true);
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w.set_m_tx_abrt(true);
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})
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},
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)
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.await;
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p.ic_clr_intr().read();
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if let Some(chunk) = chunks.next() {
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me.write_to_fifo(chunk);
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ret
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p.ic_clr_rd_req().read();
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Poll::Pending
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} else {
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let stat = p.ic_raw_intr_stat().read();
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if stat.rx_done() && stat.stop_det() {
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p.ic_clr_rx_done().read();
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p.ic_clr_stop_det().read();
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Poll::Ready(Ok(ReadStatus::Done))
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} else if stat.rd_req() && stat.tx_empty() {
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Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
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} else {
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Poll::Pending
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}
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_rx_done(true);
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w.set_m_tx_empty(true);
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w.set_m_tx_abrt(true);
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})
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},
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)
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.await
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}
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}
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/// Respond to reads with the fill byte until the controller stops asking
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/// Respond to reads with the fill byte until the controller stops asking
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@ -294,10 +356,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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let p = T::regs();
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let p = T::regs();
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let mut abort_reason = p.ic_tx_abrt_source().read();
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let mut abort_reason = p.ic_tx_abrt_source().read();
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// Mask off fifo flush count
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let tx_flush_cnt = abort_reason.tx_flush_cnt();
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abort_reason.set_tx_flush_cnt(0);
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// Mask off master_dis
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// Mask off master_dis
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abort_reason.set_abrt_master_dis(false);
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abort_reason.set_abrt_master_dis(false);
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@ -314,8 +372,8 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
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AbortReason::NoAcknowledge
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AbortReason::NoAcknowledge
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} else if abort_reason.arb_lost() {
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} else if abort_reason.arb_lost() {
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AbortReason::ArbitrationLoss
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AbortReason::ArbitrationLoss
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} else if abort_reason.abrt_slvflush_txfifo() {
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} else if abort_reason.tx_flush_cnt() > 0 {
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AbortReason::TxNotEmpty(tx_flush_cnt)
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AbortReason::TxNotEmpty(abort_reason.tx_flush_cnt())
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} else {
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} else {
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AbortReason::Other(abort_reason.0)
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AbortReason::Other(abort_reason.0)
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};
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};
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@ -110,7 +110,7 @@ async fn main(spawner: Spawner) {
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let c_sda = p.PIN_1;
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let c_sda = p.PIN_1;
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let c_scl = p.PIN_0;
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let c_scl = p.PIN_0;
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let mut config = i2c::Config::default();
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let mut config = i2c::Config::default();
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config.frequency = 5_000;
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config.frequency = 1_000_000;
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let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
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let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
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unwrap!(spawner.spawn(controller_task(controller)));
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unwrap!(spawner.spawn(controller_task(controller)));
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