stm32: update metapac

embassy-stm32/Cargo.toml

@@ -58,7 +58,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6f7449303bf8af60a63704d35df9af46006c6148" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6f7449303bf8af60a63704d35df9af46006c6148", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/src/rcc/f0.rs

@@ -127,7 +127,7 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     if config.usb_pll {
-        RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLLCLK));
+        RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
     }
     // TODO: Option to use CRS (Clock Recovery)
 
@@ -140,7 +140,7 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cfgr().modify(|w| {
             w.set_ppre(Ppre::from_bits(ppre_bits));
             w.set_hpre(Hpre::from_bits(hpre_bits));
-            w.set_sw(Sw::PLL)
+            w.set_sw(Sw::PLL1_P)
         });
     } else {
         RCC.cfgr().modify(|w| {

embassy-stm32/src/rcc/f1.rs

@@ -169,7 +169,14 @@ pub(crate) unsafe fn init(config: Config) {
         #[cfg(not(rcc_f100))]
         w.set_usbpre(Usbpre::from_bits(usbpre as u8));
         w.set_sw(if pllmul_bits.is_some() {
-            Sw::PLL
+            #[cfg(not(rcc_f1cl))]
+            {
+                Sw::PLL1_P
+            }
+            #[cfg(rcc_f1cl)]
+            {
+                Sw::PLL
+            }
         } else if config.hse.is_some() {
             Sw::HSE
         } else {

embassy-stm32/src/rcc/f2.rs

@@ -256,7 +256,7 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::PLL => {
             RCC.cr().modify(|w| w.set_pllon(true));
             while !RCC.cr().read().pllrdy() {}
-            (pll_clocks.main_freq, Sw::PLL)
+            (pll_clocks.main_freq, Sw::PLL1_P)
         }
     };
     // RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL

embassy-stm32/src/rcc/f3.rs

@@ -214,7 +214,7 @@ pub(crate) unsafe fn init(config: Config) {
     // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
     RCC.cfgr().modify(|w| {
         w.set_sw(match (pll_config, config.hse) {
-            (Some(_), _) => Sw::PLL,
+            (Some(_), _) => Sw::PLL1_P,
             (None, Some(_)) => Sw::HSE,
             (None, None) => Sw::HSI,
         })
@@ -271,7 +271,7 @@ pub(crate) unsafe fn init(config: Config) {
             pll_config.unwrap();
             assert!((pclk2 == sysclk) || (pclk2 * 2u32 == sysclk));
 
-            RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL));
+            RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL1_P));
 
             Some(sysclk * 2u32)
         }

embassy-stm32/src/rcc/f4.rs

@@ -328,7 +328,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     RCC.cfgr().modify(|w| {
         w.set_sw(if sysclk_on_pll {
-            Sw::PLL
+            Sw::PLL1_P
         } else if config.hse.is_some() {
             Sw::HSE
         } else {

embassy-stm32/src/rcc/f7.rs

@@ -247,7 +247,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     RCC.cfgr().modify(|w| {
         w.set_sw(if sysclk_on_pll {
-            Sw::PLL
+            Sw::PLL1_P
         } else if config.hse.is_some() {
             Sw::HSE
         } else {

embassy-stm32/src/rcc/l0l1.rs

@@ -131,7 +131,7 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| w.set_pllon(true));
             while !RCC.cr().read().pllrdy() {}
 
-            (freq, Sw::PLL)
+            (freq, Sw::PLL1_P)
         }
     };
 

embassy-stm32/src/rcc/l4l5.rs

@@ -187,12 +187,12 @@ pub(crate) unsafe fn init(config: Config) {
 
     let sys_clk = match config.mux {
         ClockSrc::HSE => hse.unwrap(),
-        #[cfg(rcc_l5)]
-        ClockSrc::HSI16 => hsi16.unwrap(),
-        #[cfg(not(rcc_l5))]
         ClockSrc::HSI => hsi16.unwrap(),
         ClockSrc::MSI => msi.unwrap(),
-        ClockSrc::PLL => pll._r.unwrap(),
+        #[cfg(rcc_l4)]
+        ClockSrc::PLL1_P => pll._r.unwrap(),
+        #[cfg(not(rcc_l4))]
+        ClockSrc::PLL1_R => pll._r.unwrap(),
     };
 
     #[cfg(stm32l4)]
@@ -203,9 +203,6 @@ pub(crate) unsafe fn init(config: Config) {
         Clk48Src::HSI48 => hsi48,
         Clk48Src::MSI => msi,
         Clk48Src::PLLSAI1_Q => pllsai1._q,
-        #[cfg(rcc_l5)]
-        Clk48Src::PLL_Q => pll._q,
-        #[cfg(not(rcc_l5))]
         Clk48Src::PLL1_Q => pll._q,
     };
 
@@ -363,9 +360,6 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
     let pll_src = match pll.source {
         PLLSource::NONE => panic!("must not select PLL source as NONE"),
         PLLSource::HSE => input.hse,
-        #[cfg(rcc_l5)]
-        PLLSource::HSI16 => input.hsi16,
-        #[cfg(not(rcc_l5))]
         PLLSource::HSI => input.hsi16,
         PLLSource::MSI => input.msi,
     };

examples/stm32l4/src/bin/rng.rs

@@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSI,

examples/stm32l4/src/bin/rtc.rs

@@ -15,7 +15,7 @@ use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hse = Some(Hertz::mhz(8));
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSE,

examples/stm32l4/src/bin/spe_adin1110_http_server.rs

@@ -77,7 +77,7 @@ async fn main(spawner: Spawner) {
 
     // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
     // 80MHz highest frequency for flash 0 wait.
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hse = Some(Hertz::mhz(8));
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSE,

examples/stm32l4/src/bin/usb_serial.rs

@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
 
     let mut config = Config::default();
     config.rcc.hsi48 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSI,

examples/stm32l5/src/bin/rng.rs

@@ -17,10 +17,10 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 64Mhz clock (16 / 1 * 8 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL8,
         divp: None,

examples/stm32l5/src/bin/usb_ethernet.rs

@@ -46,10 +46,10 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
 async fn main(spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_hid_mouse.rs

@@ -23,10 +23,10 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_serial.rs

@@ -21,10 +21,10 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

tests/stm32/src/common.rs

@@ -295,7 +295,14 @@ pub fn config() -> Config {
     #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.mux = ClockSrc::PLL;
+        #[cfg(feature = "stm32l4r5zi")]
+        {
+            config.rcc.mux = ClockSrc::PLL1_R;
+        }
+        #[cfg(not(feature = "stm32l4r5zi"))]
+        {
+            config.rcc.mux = ClockSrc::PLL1_P;
+        }
         config.rcc.hsi16 = true;
         config.rcc.pll = Some(Pll {
             source: PLLSource::HSI,
@@ -320,10 +327,10 @@ pub fn config() -> Config {
     {
         use embassy_stm32::rcc::*;
         config.rcc.hsi16 = true;
-        config.rcc.mux = ClockSrc::PLL;
+        config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
             // 110Mhz clock (16 / 4 * 55 / 2)
-            source: PLLSource::HSI16,
+            source: PLLSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL55,
             divp: None,