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usb: add transceiver delay option

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This commit is contained in:
Matt Ickstadt 2024-05-21 14:23:32 -05:00
parent bb82a1bd60
commit 9d6746e650
1 changed files with 15 additions and 1 deletions
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16
embassy-usb-synopsys-otg/src/lib.rs
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@ -293,11 +293,22 @@ pub struct Config {
/// If you set this to true, you must connect VBUS to PA9 for FS, PB13 for HS, possibly with a /// If you set this to true, you must connect VBUS to PA9 for FS, PB13 for HS, possibly with a
/// voltage divider. See ST application note AN4879 and the reference manual for more details. /// voltage divider. See ST application note AN4879 and the reference manual for more details.
pub vbus_detection: bool, pub vbus_detection: bool,
/// Enable transceiver delay.
///
/// Some ULPI PHYs like the Microchip USB334x series require a delay between the ULPI register write that initiates
/// the HS Chirp and the subsequent transmit command, otherwise the HS Chirp does not get executed and the deivce
/// enumerates in FS mode. Some USB Link IP like those in the STM32H7 series support adding this delay to work with
/// the affected PHYs.
pub xcvrdly: bool,
} }
impl Default for Config { impl Default for Config {
fn default() -> Self { fn default() -> Self {
Self { vbus_detection: false } Self {
vbus_detection: false,
xcvrdly: false,
}
} }
} }
@ -581,6 +592,9 @@ impl<'d, const MAX_EP_COUNT: usize> Bus<'d, MAX_EP_COUNT> {
r.dcfg().write(|w| { r.dcfg().write(|w| {
w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80); w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80);
w.set_dspd(phy_type.to_dspd()); w.set_dspd(phy_type.to_dspd());
if self.config.xcvrdly {
w.set_xcvrdly(true);
}
}); });
// Unmask transfer complete EP interrupt // Unmask transfer complete EP interrupt