diff --git a/embassy-usb-synopsys-otg/src/lib.rs b/embassy-usb-synopsys-otg/src/lib.rs
index 34dcd1497..b90e059f6 100644
--- a/embassy-usb-synopsys-otg/src/lib.rs
+++ b/embassy-usb-synopsys-otg/src/lib.rs
@@ -293,11 +293,22 @@ pub struct Config {
     /// If you set this to true, you must connect VBUS to PA9 for FS, PB13 for HS, possibly with a
     /// voltage divider. See ST application note AN4879 and the reference manual for more details.
     pub vbus_detection: bool,
+
+    /// Enable transceiver delay.
+    ///
+    /// Some ULPI PHYs like the Microchip USB334x series require a delay between the ULPI register write that initiates
+    /// the HS Chirp and the subsequent transmit command, otherwise the HS Chirp does not get executed and the deivce
+    /// enumerates in FS mode. Some USB Link IP like those in the STM32H7 series support adding this delay to work with
+    /// the affected PHYs.
+    pub xcvrdly: bool,
 }
 
 impl Default for Config {
     fn default() -> Self {
-        Self { vbus_detection: false }
+        Self {
+            vbus_detection: false,
+            xcvrdly: false,
+        }
     }
 }
 
@@ -581,6 +592,9 @@ impl<'d, const MAX_EP_COUNT: usize> Bus<'d, MAX_EP_COUNT> {
         r.dcfg().write(|w| {
             w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80);
             w.set_dspd(phy_type.to_dspd());
+            if self.config.xcvrdly {
+                w.set_xcvrdly(true);
+            }
         });
 
         // Unmask transfer complete EP interrupt