mirror of
https://github.com/embassy-rs/embassy.git
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Merge pull request #3006 from honzasp/harmonize-new
stm32: Make initialization of I2C and USART consistent with SPI
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
9856d21693
@ -9,16 +9,16 @@ use core::future::Future;
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use core::iter;
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, Peripheral};
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use embassy_hal_internal::{Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(feature = "time")]
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use embassy_time::{Duration, Instant};
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use crate::dma::ChannelAndRequest;
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use crate::gpio::{AFType, Pull};
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use crate::gpio::{AFType, AnyPin, Pull, SealedPin as _, Speed};
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use crate::interrupt::typelevel::Interrupt;
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use crate::mode::{Async, Blocking, Mode};
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use crate::rcc::{self, RccInfo, SealedRccPeripheral};
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use crate::rcc::{RccInfo, SealedRccPeripheral};
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use crate::time::Hertz;
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use crate::{interrupt, peripherals};
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@ -72,11 +72,29 @@ impl Default for Config {
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}
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}
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impl Config {
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fn scl_pull_mode(&self) -> Pull {
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match self.scl_pullup {
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true => Pull::Up,
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false => Pull::Down,
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}
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}
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fn sda_pull_mode(&self) -> Pull {
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match self.sda_pullup {
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true => Pull::Up,
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false => Pull::Down,
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}
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}
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}
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/// I2C driver.
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pub struct I2c<'d, M: Mode> {
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info: &'static Info,
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state: &'static State,
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kernel_clock: Hertz,
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scl: Option<PeripheralRef<'d, AnyPin>>,
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sda: Option<PeripheralRef<'d, AnyPin>>,
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tx_dma: Option<ChannelAndRequest<'d>>,
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rx_dma: Option<ChannelAndRequest<'d>>,
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#[cfg(feature = "time")]
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@ -98,7 +116,15 @@ impl<'d> I2c<'d, Async> {
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freq: Hertz,
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config: Config,
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) -> Self {
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Self::new_inner(peri, scl, sda, new_dma!(tx_dma), new_dma!(rx_dma), freq, config)
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Self::new_inner(
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peri,
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new_pin!(scl, AFType::OutputOpenDrain, Speed::Medium, config.scl_pull_mode()),
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new_pin!(sda, AFType::OutputOpenDrain, Speed::Medium, config.sda_pull_mode()),
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new_dma!(tx_dma),
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new_dma!(rx_dma),
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freq,
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config,
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)
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}
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}
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@ -111,7 +137,15 @@ impl<'d> I2c<'d, Blocking> {
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freq: Hertz,
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config: Config,
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) -> Self {
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Self::new_inner(peri, scl, sda, None, None, freq, config)
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Self::new_inner(
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peri,
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new_pin!(scl, AFType::OutputOpenDrain, Speed::Medium, config.scl_pull_mode()),
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new_pin!(sda, AFType::OutputOpenDrain, Speed::Medium, config.sda_pull_mode()),
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None,
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None,
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freq,
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config,
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)
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}
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}
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@ -119,34 +153,13 @@ impl<'d, M: Mode> I2c<'d, M> {
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/// Create a new I2C driver.
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fn new_inner<T: Instance>(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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scl: Option<PeripheralRef<'d, AnyPin>>,
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sda: Option<PeripheralRef<'d, AnyPin>>,
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tx_dma: Option<ChannelAndRequest<'d>>,
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rx_dma: Option<ChannelAndRequest<'d>>,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(scl, sda);
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rcc::enable_and_reset::<T>();
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scl.set_as_af_pull(
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scl.af_num(),
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AFType::OutputOpenDrain,
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match config.scl_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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sda.set_as_af_pull(
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sda.af_num(),
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AFType::OutputOpenDrain,
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match config.sda_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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unsafe { T::EventInterrupt::enable() };
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unsafe { T::ErrorInterrupt::enable() };
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@ -154,18 +167,23 @@ impl<'d, M: Mode> I2c<'d, M> {
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info: T::info(),
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state: T::state(),
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kernel_clock: T::frequency(),
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scl,
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sda,
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tx_dma,
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rx_dma,
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#[cfg(feature = "time")]
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timeout: config.timeout,
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_phantom: PhantomData,
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};
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this.init(freq, config);
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this.enable_and_init(freq, config);
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this
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}
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fn enable_and_init(&mut self, freq: Hertz, config: Config) {
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self.info.rcc.enable_and_reset();
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self.init(freq, config);
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}
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fn timeout(&self) -> Timeout {
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Timeout {
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#[cfg(feature = "time")]
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@ -174,6 +192,15 @@ impl<'d, M: Mode> I2c<'d, M> {
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}
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}
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impl<'d, M: Mode> Drop for I2c<'d, M> {
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fn drop(&mut self) {
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self.scl.as_ref().map(|x| x.set_as_disconnected());
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self.sda.as_ref().map(|x| x.set_as_disconnected());
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self.info.rcc.disable()
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}
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}
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#[derive(Copy, Clone)]
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struct Timeout {
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#[cfg(feature = "time")]
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@ -700,12 +700,6 @@ impl<'d> I2c<'d, Async> {
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}
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}
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impl<'d, M: PeriMode> Drop for I2c<'d, M> {
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fn drop(&mut self) {
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self.info.rcc.disable()
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}
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}
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enum Mode {
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Fast,
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Standard,
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@ -671,12 +671,6 @@ impl<'d> I2c<'d, Async> {
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}
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}
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impl<'d, M: Mode> Drop for I2c<'d, M> {
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fn drop(&mut self) {
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self.info.rcc.disable();
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}
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}
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/// I2C Stop Configuration
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///
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/// Peripheral options for generating the STOP condition
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@ -13,7 +13,7 @@ use crate::dma::{slice_ptr_parts, word, ChannelAndRequest};
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use crate::gpio::{AFType, AnyPin, Pull, SealedPin as _, Speed};
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use crate::mode::{Async, Blocking, Mode as PeriMode};
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use crate::pac::spi::{regs, vals, Spi as Regs};
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use crate::rcc::{self, RccInfo, SealedRccPeripheral};
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use crate::rcc::{RccInfo, SealedRccPeripheral};
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use crate::time::Hertz;
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use crate::Peripheral;
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@ -120,17 +120,30 @@ impl<'d, M: PeriMode> Spi<'d, M> {
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rx_dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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) -> Self {
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let regs = T::info().regs;
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let kernel_clock = T::frequency();
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let br = compute_baud_rate(kernel_clock, config.frequency);
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let mut this = Self {
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info: T::info(),
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kernel_clock: T::frequency(),
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sck,
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mosi,
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miso,
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tx_dma,
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rx_dma,
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current_word_size: <u8 as SealedWord>::CONFIG,
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_phantom: PhantomData,
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};
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this.enable_and_init(config);
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this
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}
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fn enable_and_init(&mut self, config: Config) {
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let br = compute_baud_rate(self.kernel_clock, config.frequency);
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let cpha = config.raw_phase();
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let cpol = config.raw_polarity();
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let lsbfirst = config.raw_byte_order();
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rcc::enable_and_reset::<T>();
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self.info.rcc.enable_and_reset();
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let regs = self.info.regs;
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#[cfg(any(spi_v1, spi_f1))]
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{
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regs.cr2().modify(|w| {
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@ -209,18 +222,6 @@ impl<'d, M: PeriMode> Spi<'d, M> {
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w.set_spe(true);
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});
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}
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Self {
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info: T::info(),
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kernel_clock,
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sck,
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mosi,
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miso,
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tx_dma,
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rx_dma,
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current_word_size: <u8 as SealedWord>::CONFIG,
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_phantom: PhantomData,
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}
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}
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/// Reconfigures it with the supplied config.
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@ -611,7 +612,7 @@ impl<'d> Spi<'d, Async> {
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// see RM0453 rev 1 section 7.2.13 page 291
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// The SUBGHZSPI_SCK frequency is obtained by PCLK3 divided by two.
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// The SUBGHZSPI_SCK clock maximum speed must not exceed 16 MHz.
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let pclk3_freq = <crate::peripherals::SUBGHZSPI as crate::rcc::SealedRccPeripheral>::frequency().0;
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let pclk3_freq = <crate::peripherals::SUBGHZSPI as SealedRccPeripheral>::frequency().0;
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let freq = Hertz(core::cmp::min(pclk3_freq / 2, 16_000_000));
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let mut config = Config::default();
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config.mode = MODE_0;
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@ -6,7 +6,7 @@ use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
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use embassy_hal_internal::{into_ref, Peripheral};
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use embassy_hal_internal::{Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(not(any(usart_v1, usart_v2)))]
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@ -15,10 +15,8 @@ use super::{
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clear_interrupt_flags, configure, rdr, reconfigure, sr, tdr, Config, ConfigError, CtsPin, Error, Info, Instance,
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Regs, RtsPin, RxPin, TxPin,
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};
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use crate::gpio::AFType;
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use crate::interrupt::typelevel::Interrupt as _;
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use crate::gpio::{AFType, AnyPin, SealedPin as _};
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use crate::interrupt::{self, InterruptExt};
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use crate::rcc;
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use crate::time::Hertz;
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/// Interrupt handler.
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@ -156,7 +154,9 @@ pub struct BufferedUartTx<'d> {
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info: &'static Info,
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state: &'static State,
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kernel_clock: Hertz,
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_phantom: PhantomData<&'d mut ()>,
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tx: Option<PeripheralRef<'d, AnyPin>>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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de: Option<PeripheralRef<'d, AnyPin>>,
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}
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/// Rx-only buffered UART
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@ -166,7 +166,8 @@ pub struct BufferedUartRx<'d> {
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info: &'static Info,
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state: &'static State,
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kernel_clock: Hertz,
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_phantom: PhantomData<&'d mut ()>,
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rx: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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}
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impl<'d> SetConfig for BufferedUart<'d> {
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@ -207,9 +208,17 @@ impl<'d> BufferedUart<'d> {
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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Self::new_inner(
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peri,
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new_pin!(rx, AFType::Input),
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new_pin!(tx, AFType::OutputPushPull),
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None,
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None,
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None,
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tx_buffer,
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rx_buffer,
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config,
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)
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}
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/// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
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@ -224,18 +233,17 @@ impl<'d> BufferedUart<'d> {
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(cts, rts);
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rcc::enable_and_reset::<T>();
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rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
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cts.set_as_af(cts.af_num(), AFType::Input);
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T::info().regs.cr3().write(|w| {
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w.set_rtse(true);
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w.set_ctse(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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Self::new_inner(
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peri,
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new_pin!(rx, AFType::Input),
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new_pin!(tx, AFType::OutputPushPull),
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new_pin!(rts, AFType::OutputPushPull),
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new_pin!(cts, AFType::Input),
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None,
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tx_buffer,
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rx_buffer,
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config,
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)
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}
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/// Create a new bidirectional buffered UART driver with a driver-enable pin
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@ -250,66 +258,89 @@ impl<'d> BufferedUart<'d> {
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(de);
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rcc::enable_and_reset::<T>();
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de.set_as_af(de.af_num(), AFType::OutputPushPull);
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T::info().regs.cr3().write(|w| {
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w.set_dem(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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Self::new_inner(
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peri,
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new_pin!(rx, AFType::Input),
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new_pin!(tx, AFType::OutputPushPull),
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None,
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None,
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new_pin!(de, AFType::OutputPushPull),
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tx_buffer,
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rx_buffer,
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config,
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)
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}
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|
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fn new_inner<T: Instance>(
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_peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: Option<PeripheralRef<'d, AnyPin>>,
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tx: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
|
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cts: Option<PeripheralRef<'d, AnyPin>>,
|
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de: Option<PeripheralRef<'d, AnyPin>>,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(_peri, rx, tx);
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let info = T::info();
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let state = T::buffered_state();
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let kernel_clock = T::frequency();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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let r = info.regs;
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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|
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configure(info, kernel_clock, &config, true, true)?;
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|
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r.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
|
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});
|
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|
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
|
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|
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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|
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Ok(Self {
|
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let mut this = Self {
|
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rx: BufferedUartRx {
|
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info,
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state,
|
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kernel_clock,
|
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_phantom: PhantomData,
|
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rx,
|
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rts,
|
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},
|
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tx: BufferedUartTx {
|
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info,
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state,
|
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kernel_clock,
|
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_phantom: PhantomData,
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tx,
|
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cts,
|
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de,
|
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},
|
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})
|
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};
|
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this.enable_and_configure(tx_buffer, rx_buffer, &config)?;
|
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Ok(this)
|
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}
|
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|
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fn enable_and_configure(
|
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&mut self,
|
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tx_buffer: &'d mut [u8],
|
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rx_buffer: &'d mut [u8],
|
||||
config: &Config,
|
||||
) -> Result<(), ConfigError> {
|
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let info = self.rx.info;
|
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let state = self.rx.state;
|
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
|
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|
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info.rcc.enable_and_reset();
|
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|
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let len = tx_buffer.len();
|
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
|
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let len = rx_buffer.len();
|
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
|
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|
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info.regs.cr3().write(|w| {
|
||||
w.set_rtse(self.rx.rts.is_some());
|
||||
w.set_ctse(self.tx.cts.is_some());
|
||||
#[cfg(not(any(usart_v1, usart_v2)))]
|
||||
w.set_dem(self.tx.de.is_some());
|
||||
});
|
||||
configure(info, self.rx.kernel_clock, &config, true, true)?;
|
||||
|
||||
info.regs.cr1().modify(|w| {
|
||||
w.set_rxneie(true);
|
||||
w.set_idleie(true);
|
||||
});
|
||||
|
||||
info.interrupt.unpend();
|
||||
unsafe { info.interrupt.enable() };
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Split the driver into a Tx and Rx part (useful for sending to separate tasks)
|
||||
@ -516,6 +547,8 @@ impl<'d> Drop for BufferedUartRx<'d> {
|
||||
}
|
||||
}
|
||||
|
||||
self.rx.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.rts.as_ref().map(|x| x.set_as_disconnected());
|
||||
drop_tx_rx(self.info, state);
|
||||
}
|
||||
}
|
||||
@ -533,6 +566,9 @@ impl<'d> Drop for BufferedUartTx<'d> {
|
||||
}
|
||||
}
|
||||
|
||||
self.tx.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.cts.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.de.as_ref().map(|x| x.set_as_disconnected());
|
||||
drop_tx_rx(self.info, state);
|
||||
}
|
||||
}
|
||||
|
||||
@ -14,7 +14,7 @@ use embassy_sync::waitqueue::AtomicWaker;
|
||||
use futures_util::future::{select, Either};
|
||||
|
||||
use crate::dma::ChannelAndRequest;
|
||||
use crate::gpio::{AFType, AnyPin, SealedPin};
|
||||
use crate::gpio::{AFType, AnyPin, SealedPin as _};
|
||||
use crate::interrupt::typelevel::Interrupt as _;
|
||||
use crate::interrupt::{self, Interrupt, InterruptExt};
|
||||
use crate::mode::{Async, Blocking, Mode};
|
||||
@ -28,7 +28,7 @@ use crate::pac::usart::Lpuart as Regs;
|
||||
#[cfg(any(usart_v1, usart_v2))]
|
||||
use crate::pac::usart::Usart as Regs;
|
||||
use crate::pac::usart::{regs, vals};
|
||||
use crate::rcc::{self, RccInfo, SealedRccPeripheral};
|
||||
use crate::rcc::{RccInfo, SealedRccPeripheral};
|
||||
use crate::time::Hertz;
|
||||
use crate::Peripheral;
|
||||
|
||||
@ -429,29 +429,33 @@ impl<'d, M: Mode> UartTx<'d, M> {
|
||||
tx_dma: Option<ChannelAndRequest<'d>>,
|
||||
config: Config,
|
||||
) -> Result<Self, ConfigError> {
|
||||
rcc::enable_and_reset::<T>();
|
||||
|
||||
let info = T::info();
|
||||
let state = T::state();
|
||||
let kernel_clock = T::frequency();
|
||||
let r = info.regs;
|
||||
r.cr3().modify(|w| {
|
||||
w.set_ctse(cts.is_some());
|
||||
});
|
||||
configure(info, kernel_clock, &config, false, true)?;
|
||||
|
||||
state.tx_rx_refcount.store(1, Ordering::Relaxed);
|
||||
|
||||
Ok(Self {
|
||||
info,
|
||||
state,
|
||||
kernel_clock,
|
||||
let mut this = Self {
|
||||
info: T::info(),
|
||||
state: T::state(),
|
||||
kernel_clock: T::frequency(),
|
||||
tx,
|
||||
cts,
|
||||
de: None,
|
||||
tx_dma,
|
||||
_phantom: PhantomData,
|
||||
})
|
||||
};
|
||||
this.enable_and_configure(&config)?;
|
||||
Ok(this)
|
||||
}
|
||||
|
||||
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
|
||||
let info = self.info;
|
||||
let state = self.state;
|
||||
state.tx_rx_refcount.store(1, Ordering::Relaxed);
|
||||
|
||||
info.rcc.enable_and_reset();
|
||||
|
||||
info.regs.cr3().modify(|w| {
|
||||
w.set_ctse(self.cts.is_some());
|
||||
});
|
||||
configure(info, self.kernel_clock, config, false, true)?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Reconfigure the driver
|
||||
@ -775,34 +779,38 @@ impl<'d, M: Mode> UartRx<'d, M> {
|
||||
rx_dma: Option<ChannelAndRequest<'d>>,
|
||||
config: Config,
|
||||
) -> Result<Self, ConfigError> {
|
||||
rcc::enable_and_reset::<T>();
|
||||
|
||||
let info = T::info();
|
||||
let state = T::state();
|
||||
let kernel_clock = T::frequency();
|
||||
let r = info.regs;
|
||||
r.cr3().write(|w| {
|
||||
w.set_rtse(rts.is_some());
|
||||
});
|
||||
configure(info, kernel_clock, &config, true, false)?;
|
||||
|
||||
T::Interrupt::unpend();
|
||||
unsafe { T::Interrupt::enable() };
|
||||
|
||||
state.tx_rx_refcount.store(1, Ordering::Relaxed);
|
||||
|
||||
Ok(Self {
|
||||
let mut this = Self {
|
||||
_phantom: PhantomData,
|
||||
info,
|
||||
state,
|
||||
kernel_clock,
|
||||
info: T::info(),
|
||||
state: T::state(),
|
||||
kernel_clock: T::frequency(),
|
||||
rx,
|
||||
rts,
|
||||
rx_dma,
|
||||
detect_previous_overrun: config.detect_previous_overrun,
|
||||
#[cfg(any(usart_v1, usart_v2))]
|
||||
buffered_sr: stm32_metapac::usart::regs::Sr(0),
|
||||
})
|
||||
};
|
||||
this.enable_and_configure(&config)?;
|
||||
Ok(this)
|
||||
}
|
||||
|
||||
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
|
||||
let info = self.info;
|
||||
let state = self.state;
|
||||
state.tx_rx_refcount.store(1, Ordering::Relaxed);
|
||||
|
||||
info.rcc.enable_and_reset();
|
||||
|
||||
info.regs.cr3().write(|w| {
|
||||
w.set_rtse(self.rts.is_some());
|
||||
});
|
||||
configure(info, self.kernel_clock, &config, true, false)?;
|
||||
|
||||
info.interrupt.unpend();
|
||||
unsafe { info.interrupt.enable() };
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Reconfigure the driver
|
||||
@ -1228,27 +1236,11 @@ impl<'d, M: Mode> Uart<'d, M> {
|
||||
rx_dma: Option<ChannelAndRequest<'d>>,
|
||||
config: Config,
|
||||
) -> Result<Self, ConfigError> {
|
||||
rcc::enable_and_reset::<T>();
|
||||
|
||||
let info = T::info();
|
||||
let state = T::state();
|
||||
let kernel_clock = T::frequency();
|
||||
let r = info.regs;
|
||||
|
||||
r.cr3().write(|w| {
|
||||
w.set_rtse(rts.is_some());
|
||||
w.set_ctse(cts.is_some());
|
||||
#[cfg(not(any(usart_v1, usart_v2)))]
|
||||
w.set_dem(de.is_some());
|
||||
});
|
||||
configure(info, kernel_clock, &config, true, true)?;
|
||||
|
||||
T::Interrupt::unpend();
|
||||
unsafe { T::Interrupt::enable() };
|
||||
|
||||
state.tx_rx_refcount.store(2, Ordering::Relaxed);
|
||||
|
||||
Ok(Self {
|
||||
let mut this = Self {
|
||||
tx: UartTx {
|
||||
_phantom: PhantomData,
|
||||
info,
|
||||
@ -1271,7 +1263,30 @@ impl<'d, M: Mode> Uart<'d, M> {
|
||||
#[cfg(any(usart_v1, usart_v2))]
|
||||
buffered_sr: stm32_metapac::usart::regs::Sr(0),
|
||||
},
|
||||
})
|
||||
};
|
||||
this.enable_and_configure(&config)?;
|
||||
Ok(this)
|
||||
}
|
||||
|
||||
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
|
||||
let info = self.rx.info;
|
||||
let state = self.rx.state;
|
||||
state.tx_rx_refcount.store(2, Ordering::Relaxed);
|
||||
|
||||
info.rcc.enable_and_reset();
|
||||
|
||||
info.regs.cr3().write(|w| {
|
||||
w.set_rtse(self.rx.rts.is_some());
|
||||
w.set_ctse(self.tx.cts.is_some());
|
||||
#[cfg(not(any(usart_v1, usart_v2)))]
|
||||
w.set_dem(self.tx.de.is_some());
|
||||
});
|
||||
configure(info, self.rx.kernel_clock, config, true, true)?;
|
||||
|
||||
info.interrupt.unpend();
|
||||
unsafe { info.interrupt.enable() };
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Perform a blocking write
|
||||
|
||||
@ -4,10 +4,12 @@ use core::sync::atomic::{compiler_fence, Ordering};
|
||||
use core::task::Poll;
|
||||
|
||||
use embassy_embedded_hal::SetConfig;
|
||||
use embassy_hal_internal::PeripheralRef;
|
||||
use futures_util::future::{select, Either};
|
||||
|
||||
use super::{clear_interrupt_flags, rdr, reconfigure, sr, Config, ConfigError, Error, Info, State, UartRx};
|
||||
use crate::dma::ReadableRingBuffer;
|
||||
use crate::gpio::{AnyPin, SealedPin as _};
|
||||
use crate::mode::Async;
|
||||
use crate::time::Hertz;
|
||||
use crate::usart::{Regs, Sr};
|
||||
@ -19,6 +21,8 @@ pub struct RingBufferedUartRx<'d> {
|
||||
info: &'static Info,
|
||||
state: &'static State,
|
||||
kernel_clock: Hertz,
|
||||
rx: Option<PeripheralRef<'d, AnyPin>>,
|
||||
rts: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ring_buf: ReadableRingBuffer<'d, u8>,
|
||||
}
|
||||
|
||||
@ -49,6 +53,8 @@ impl<'d> UartRx<'d, Async> {
|
||||
let state = self.state;
|
||||
let kernel_clock = self.kernel_clock;
|
||||
let ring_buf = unsafe { ReadableRingBuffer::new(rx_dma, request, rdr(info.regs), dma_buf, opts) };
|
||||
let rx = unsafe { self.rx.as_ref().map(|x| x.clone_unchecked()) };
|
||||
let rts = unsafe { self.rts.as_ref().map(|x| x.clone_unchecked()) };
|
||||
|
||||
// Don't disable the clock
|
||||
mem::forget(self);
|
||||
@ -57,6 +63,8 @@ impl<'d> UartRx<'d, Async> {
|
||||
info,
|
||||
state,
|
||||
kernel_clock,
|
||||
rx,
|
||||
rts,
|
||||
ring_buf,
|
||||
}
|
||||
}
|
||||
@ -221,6 +229,8 @@ impl<'d> RingBufferedUartRx<'d> {
|
||||
impl Drop for RingBufferedUartRx<'_> {
|
||||
fn drop(&mut self) {
|
||||
self.teardown_uart();
|
||||
self.rx.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.rts.as_ref().map(|x| x.set_as_disconnected());
|
||||
super::drop_tx_rx(self.info, self.state);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user