stm32/usart: set refcount even if initialization failed

This commit is contained in:
Jan Špaček 2024-06-03 20:12:33 +02:00
parent 664e4a5c03
commit f3703ff6bf
2 changed files with 4 additions and 4 deletions

View File

@ -315,6 +315,7 @@ impl<'d> BufferedUart<'d> {
) -> Result<(), ConfigError> {
let info = self.rx.info;
let state = self.rx.state;
state.tx_rx_refcount.store(2, Ordering::Relaxed);
info.rcc.enable_and_reset();
@ -339,7 +340,6 @@ impl<'d> BufferedUart<'d> {
info.interrupt.unpend();
unsafe { info.interrupt.enable() };
state.tx_rx_refcount.store(2, Ordering::Relaxed);
Ok(())
}

View File

@ -446,6 +446,7 @@ impl<'d, M: Mode> UartTx<'d, M> {
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
let info = self.info;
let state = self.state;
state.tx_rx_refcount.store(1, Ordering::Relaxed);
info.rcc.enable_and_reset();
@ -454,7 +455,6 @@ impl<'d, M: Mode> UartTx<'d, M> {
});
configure(info, self.kernel_clock, config, false, true)?;
state.tx_rx_refcount.store(1, Ordering::Relaxed);
Ok(())
}
@ -798,6 +798,7 @@ impl<'d, M: Mode> UartRx<'d, M> {
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
let info = self.info;
let state = self.state;
state.tx_rx_refcount.store(1, Ordering::Relaxed);
info.rcc.enable_and_reset();
@ -809,7 +810,6 @@ impl<'d, M: Mode> UartRx<'d, M> {
info.interrupt.unpend();
unsafe { info.interrupt.enable() };
state.tx_rx_refcount.store(1, Ordering::Relaxed);
Ok(())
}
@ -1271,6 +1271,7 @@ impl<'d, M: Mode> Uart<'d, M> {
fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
let info = self.rx.info;
let state = self.rx.state;
state.tx_rx_refcount.store(2, Ordering::Relaxed);
info.rcc.enable_and_reset();
@ -1285,7 +1286,6 @@ impl<'d, M: Mode> Uart<'d, M> {
info.interrupt.unpend();
unsafe { info.interrupt.enable() };
state.tx_rx_refcount.store(2, Ordering::Relaxed);
Ok(())
}