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rp: fix watchdog CTRL register getting overwritten

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Nick 2024-05-29 06:29:25 +01:00
parent 000b022ae2
commit 9031ce7fa7
1 changed files with 2 additions and 2 deletions
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4
embassy-rp/src/watchdog.rs
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@ -46,7 +46,7 @@ impl Watchdog {
/// or when JTAG is accessing bus fabric
pub fn pause_on_debug(&mut self, pause: bool) {
let watchdog = pac::WATCHDOG;
watchdog.ctrl().write(|w| {
watchdog.ctrl().modify(|w| {
w.set_pause_dbg0(pause);
w.set_pause_dbg1(pause);
w.set_pause_jtag(pause);
@ -60,7 +60,7 @@ impl Watchdog {
fn enable(&self, bit: bool) {
let watchdog = pac::WATCHDOG;
watchdog.ctrl().write(|w| w.set_enable(bit))
watchdog.ctrl().modify(|w| w.set_enable(bit))
}
// Configure which hardware will be reset by the watchdog