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Merge pull request #3538 from elagil/sai_flush_fifo_on_disable
Flush SAI FIFO on init and disable
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commit
6c4b3d82b6
@ -861,12 +861,15 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
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ring_buffer: RingBuffer<'d, W>,
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config: Config,
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) -> Self {
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let ch = T::REGS.ch(sub_block as usize);
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#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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{
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let ch = T::REGS.ch(sub_block as usize);
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ch.cr1().modify(|w| w.set_saien(false));
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}
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ch.cr2().modify(|w| w.set_fflush(true));
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#[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
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{
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if let SyncInput::External(i) = config.sync_input {
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@ -888,7 +891,6 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
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#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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{
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let ch = T::REGS.ch(sub_block as usize);
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ch.cr1().modify(|w| {
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w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
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TxRx::Transmitter
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@ -1045,6 +1047,7 @@ impl<'d, T: Instance, W: word::Word> Drop for Sai<'d, T, W> {
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fn drop(&mut self) {
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let ch = T::REGS.ch(self.sub_block as usize);
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ch.cr1().modify(|w| w.set_saien(false));
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ch.cr2().modify(|w| w.set_fflush(true));
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self.fs.as_ref().map(|x| x.set_as_disconnected());
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self.sd.as_ref().map(|x| x.set_as_disconnected());
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self.sck.as_ref().map(|x| x.set_as_disconnected());
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