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Merge pull request #3539 from embassy-rs/update-nrf-pac

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Update nrf-pac.
This commit is contained in:
Dario Nieuwenhuis 2024-11-15 01:25:48 +00:00 committed by GitHub
commit fe79af5614
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GPG Key ID: B5690EEEBB952194
36 changed files with 641 additions and 868 deletions
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2
embassy-net-nrf91/Cargo.toml
View File

@ -17,7 +17,7 @@ log = [ "dep:log" ]
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "875a29629cc1c87aae00cfea647a956b3807d8be" }
nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "12e2461859acb0bfea9b2ef5cd73f1283c139ac0" }
cortex-m = "0.7.7"
embassy-time = { version = "0.3.1", path = "../embassy-time" }

2
embassy-nrf/Cargo.toml
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@ -136,7 +136,7 @@ embedded-hal-async = { version = "1.0" }
embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.1" }
nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "875a29629cc1c87aae00cfea647a956b3807d8be" }
nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "12e2461859acb0bfea9b2ef5cd73f1283c139ac0" }
defmt = { version = "0.3", optional = true }
bitflags = "2.4.2"

8
embassy-nrf/src/chips/nrf51.rs
View File

@ -146,11 +146,11 @@ impl_pin!(P0_31, 0, 31);
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UART0,
SPI0_TWI0,
SPI1_TWI1,
TWISPI0,
TWISPI1,
GPIOTE,
ADC,
TIMER0,
@ -160,7 +160,7 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,

28
embassy-nrf/src/chips/nrf52805.rs
View File

@ -138,15 +138,15 @@ embassy_hal_internal::peripherals! {
EGU1,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
impl_spim!(SPI0, SPIM0, SPI0);
impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
impl_spis!(SPI0, SPIS0, SPI0);
impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
impl_twim!(TWI0, TWIM0, TWI0);
impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0);
impl_twis!(TWI0, TWIS0, TWI0);
impl_qdec!(QDEC, QDEC, QDEC);
@ -218,15 +218,15 @@ impl_saadc_input!(P0_05, ANALOG_INPUT3);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0,
SPIM0_SPIS0_SPI0,
UARTE0,
TWI0,
SPI0,
GPIOTE,
SAADC,
TIMER0,
@ -236,12 +236,12 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
SWI0_EGU0,
SWI1_EGU1,
EGU0_SWI0,
EGU1_SWI1,
SWI2,
SWI3,
SWI4,

28
embassy-nrf/src/chips/nrf52810.rs
View File

@ -144,15 +144,15 @@ embassy_hal_internal::peripherals! {
EGU1,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
impl_spim!(SPI0, SPIM0, SPI0);
impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
impl_spis!(SPI0, SPIS0, SPI0);
impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
impl_twim!(TWI0, TWIM0, TWI0);
impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0);
impl_twis!(TWI0, TWIS0, TWI0);
impl_pwm!(PWM0, PWM0, PWM0);
@ -244,15 +244,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0,
SPIM0_SPIS0_SPI0,
UARTE0,
TWI0,
SPI0,
GPIOTE,
SAADC,
TIMER0,
@ -262,13 +262,13 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
EGU0_SWI0,
EGU1_SWI1,
SWI2,
SWI3,
SWI4,

36
embassy-nrf/src/chips/nrf52811.rs
View File

@ -27,8 +27,8 @@ embassy_hal_internal::peripherals! {
UARTE0,
// SPI/TWI
TWISPI0,
SPI1,
TWI0_SPI1,
SPI0,
// SAADC
SAADC,
@ -144,17 +144,17 @@ embassy_hal_internal::peripherals! {
EGU1,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1);
impl_spim!(SPI0, SPIM0, SPI0);
impl_spim!(TWI0_SPI1, SPIM1, TWI0_SPI1);
impl_spis!(TWISPI0, SPIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
impl_spis!(SPI1, SPIS1, SPIM1_SPIS1_SPI1);
impl_spis!(SPI0, SPIS0, SPI0);
impl_spis!(TWI0_SPI1, SPIS1, TWI0_SPI1);
impl_twim!(TWISPI0, TWIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
impl_twim!(TWI0_SPI1, TWIM0, TWI0_SPI1);
impl_twis!(TWISPI0, TWIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
impl_twis!(TWI0_SPI1, TWIS0, TWI0_SPI1);
impl_pwm!(PWM0, PWM0, PWM0);
@ -246,15 +246,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0,
SPIM1_SPIS1_SPI1,
UARTE0,
TWI0_SPI1,
SPI0,
GPIOTE,
SAADC,
TIMER0,
@ -264,13 +264,13 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
EGU0_SWI0,
EGU1_SWI1,
SWI2,
SWI3,
SWI4,

52
embassy-nrf/src/chips/nrf52820.rs
View File

@ -145,19 +145,19 @@ embassy_hal_internal::peripherals! {
impl_usb!(USBD, USBD, USBD);
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(TWISPI0, SPIM0, TWISPI0);
impl_spim!(TWISPI1, SPIM1, TWISPI1);
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spis!(TWISPI0, SPIS0, TWISPI0);
impl_spis!(TWISPI1, SPIS1, TWISPI1);
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twim!(TWISPI0, TWIM0, TWISPI0);
impl_twim!(TWISPI1, TWIM1, TWISPI1);
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twis!(TWISPI0, TWIS0, TWISPI0);
impl_twis!(TWISPI1, TWIS1, TWISPI1);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
@ -237,19 +237,19 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU2, EGU2, SWI2_EGU2);
impl_egu!(EGU3, EGU3, SWI3_EGU3);
impl_egu!(EGU4, EGU4, SWI4_EGU4);
impl_egu!(EGU5, EGU5, SWI5_EGU5);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
impl_egu!(EGU2, EGU2, EGU2_SWI2);
impl_egu!(EGU3, EGU3, EGU3_SWI3);
impl_egu!(EGU4, EGU4, EGU4_SWI4);
impl_egu!(EGU5, EGU5, EGU5_SWI5);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
UARTE0,
TWISPI0,
TWISPI1,
GPIOTE,
TIMER0,
TIMER1,
@ -258,17 +258,17 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
EGU0_SWI0,
EGU1_SWI1,
EGU2_SWI2,
EGU3_SWI3,
EGU4_SWI4,
EGU5_SWI5,
TIMER3,
USBD,
);

60
embassy-nrf/src/chips/nrf52832.rs
View File

@ -163,21 +163,21 @@ embassy_hal_internal::peripherals! {
EGU5,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_spim!(TWISPI0, SPIM0, TWISPI0);
impl_spim!(TWISPI1, SPIM1, TWISPI1);
impl_spim!(SPI2, SPIM2, SPI2);
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
impl_spis!(TWISPI0, SPIS0, TWISPI0);
impl_spis!(TWISPI1, SPIS1, TWISPI1);
impl_spis!(SPI2, SPIS2, SPI2);
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twim!(TWISPI0, TWIM0, TWISPI0);
impl_twim!(TWISPI1, TWIM1, TWISPI1);
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twis!(TWISPI0, TWIS0, TWISPI0);
impl_twis!(TWISPI1, TWIS1, TWISPI1);
impl_pwm!(PWM0, PWM0, PWM0);
impl_pwm!(PWM1, PWM1, PWM1);
@ -277,19 +277,19 @@ impl_i2s!(I2S, I2S, I2S);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU2, EGU2, SWI2_EGU2);
impl_egu!(EGU3, EGU3, SWI3_EGU3);
impl_egu!(EGU4, EGU4, SWI4_EGU4);
impl_egu!(EGU5, EGU5, SWI5_EGU5);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
impl_egu!(EGU2, EGU2, EGU2_SWI2);
impl_egu!(EGU3, EGU3, EGU3_SWI3);
impl_egu!(EGU4, EGU4, EGU4_SWI4);
impl_egu!(EGU5, EGU5, EGU5_SWI5);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
UARTE0,
TWISPI0,
TWISPI1,
NFCT,
GPIOTE,
SAADC,
@ -300,17 +300,17 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
EGU0_SWI0,
EGU1_SWI1,
EGU2_SWI2,
EGU3_SWI3,
EGU4_SWI4,
EGU5_SWI5,
TIMER3,
TIMER4,
PWM0,
@ -318,8 +318,8 @@ embassy_hal_internal::interrupt_mod!(
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
SPI2,
RTC2,
FPU,
I2S,
FPU,
);

60
embassy-nrf/src/chips/nrf52833.rs
View File

@ -185,23 +185,23 @@ embassy_hal_internal::peripherals! {
impl_usb!(USBD, USBD, USBD);
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_uarte!(UARTE1, UARTE1, UARTE1);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_spim!(TWISPI0, SPIM0, TWISPI0);
impl_spim!(TWISPI1, SPIM1, TWISPI1);
impl_spim!(SPI2, SPIM2, SPI2);
impl_spim!(SPI3, SPIM3, SPIM3);
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
impl_spis!(TWISPI0, SPIS0, TWISPI0);
impl_spis!(TWISPI1, SPIS1, TWISPI1);
impl_spis!(SPI2, SPIS2, SPI2);
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twim!(TWISPI0, TWIM0, TWISPI0);
impl_twim!(TWISPI1, TWIM1, TWISPI1);
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twis!(TWISPI0, TWIS0, TWISPI0);
impl_twis!(TWISPI1, TWIS1, TWISPI1);
impl_pwm!(PWM0, PWM0, PWM0);
impl_pwm!(PWM1, PWM1, PWM1);
@ -319,19 +319,19 @@ impl_i2s!(I2S, I2S, I2S);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU2, EGU2, SWI2_EGU2);
impl_egu!(EGU3, EGU3, SWI3_EGU3);
impl_egu!(EGU4, EGU4, SWI4_EGU4);
impl_egu!(EGU5, EGU5, SWI5_EGU5);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
impl_egu!(EGU2, EGU2, EGU2_SWI2);
impl_egu!(EGU3, EGU3, EGU3_SWI3);
impl_egu!(EGU4, EGU4, EGU4_SWI4);
impl_egu!(EGU5, EGU5, EGU5_SWI5);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
UARTE0,
TWISPI0,
TWISPI1,
NFCT,
GPIOTE,
SAADC,
@ -342,17 +342,17 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
EGU0_SWI0,
EGU1_SWI1,
EGU2_SWI2,
EGU3_SWI3,
EGU4_SWI4,
EGU5_SWI5,
TIMER3,
TIMER4,
PWM0,
@ -360,12 +360,12 @@ embassy_hal_internal::interrupt_mod!(
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
SPI2,
RTC2,
I2S,
FPU,
USBD,
UARTE1,
PWM3,
SPIM3,
I2S,
);

60
embassy-nrf/src/chips/nrf52840.rs
View File

@ -188,23 +188,23 @@ embassy_hal_internal::peripherals! {
impl_usb!(USBD, USBD, USBD);
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE0, UARTE0, UARTE0);
impl_uarte!(UARTE1, UARTE1, UARTE1);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_spim!(TWISPI0, SPIM0, TWISPI0);
impl_spim!(TWISPI1, SPIM1, TWISPI1);
impl_spim!(SPI2, SPIM2, SPI2);
impl_spim!(SPI3, SPIM3, SPIM3);
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
impl_spis!(TWISPI0, SPIS0, TWISPI0);
impl_spis!(TWISPI1, SPIS1, TWISPI1);
impl_spis!(SPI2, SPIS2, SPI2);
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twim!(TWISPI0, TWIM0, TWISPI0);
impl_twim!(TWISPI1, TWIM1, TWISPI1);
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_twis!(TWISPI0, TWIS0, TWISPI0);
impl_twis!(TWISPI1, TWIS1, TWISPI1);
impl_pwm!(PWM0, PWM0, PWM0);
impl_pwm!(PWM1, PWM1, PWM1);
@ -324,19 +324,19 @@ impl_i2s!(I2S, I2S, I2S);
impl_radio!(RADIO, RADIO, RADIO);
impl_egu!(EGU0, EGU0, SWI0_EGU0);
impl_egu!(EGU1, EGU1, SWI1_EGU1);
impl_egu!(EGU2, EGU2, SWI2_EGU2);
impl_egu!(EGU3, EGU3, SWI3_EGU3);
impl_egu!(EGU4, EGU4, SWI4_EGU4);
impl_egu!(EGU5, EGU5, SWI5_EGU5);
impl_egu!(EGU0, EGU0, EGU0_SWI0);
impl_egu!(EGU1, EGU1, EGU1_SWI1);
impl_egu!(EGU2, EGU2, EGU2_SWI2);
impl_egu!(EGU3, EGU3, EGU3_SWI3);
impl_egu!(EGU4, EGU4, EGU4_SWI4);
impl_egu!(EGU5, EGU5, EGU5_SWI5);
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
CLOCK_POWER,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
UARTE0,
TWISPI0,
TWISPI1,
NFCT,
GPIOTE,
SAADC,
@ -347,17 +347,17 @@ embassy_hal_internal::interrupt_mod!(
TEMP,
RNG,
ECB,
CCM_AAR,
AAR_CCM,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
EGU0_SWI0,
EGU1_SWI1,
EGU2_SWI2,
EGU3_SWI3,
EGU4_SWI4,
EGU5_SWI5,
TIMER3,
TIMER4,
PWM0,
@ -365,8 +365,9 @@ embassy_hal_internal::interrupt_mod!(
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
SPI2,
RTC2,
I2S,
FPU,
USBD,
UARTE1,
@ -374,5 +375,4 @@ embassy_hal_internal::interrupt_mod!(
CRYPTOCELL,
PWM3,
SPIM3,
I2S,
);

369
embassy-nrf/src/chips/nrf5340_app.rs
View File

@ -2,229 +2,158 @@
#[allow(unused_imports)]
#[rustfmt::skip]
pub mod pac {
// The nRF5340 has a secure and non-secure (NS) mode.
// To avoid cfg spam, we remove _ns or _s suffixes here.
#[cfg(feature="rt")]
pub use nrf_pac::NVIC_PRIO_BITS;
pub use nrf_pac::{common, shared};
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf_pac::interrupt;
#[doc(no_inline)]
pub use nrf_pac::{
Interrupt,
cache_s as cache,
cachedata_s as cachedata,
cacheinfo_s as cacheinfo,
clock_ns as clock,
comp_ns as comp,
cryptocell_s as cryptocell,
cti_s as cti,
ctrlap_ns as ctrlap,
dcnf_ns as dcnf,
dppic_ns as dppic,
egu_ns as egu,
ficr_s as ficr,
fpu_ns as fpu,
gpiote_s as gpiote,
i2s_ns as i2s,
ipc_ns as ipc,
kmu_ns as kmu,
lpcomp_ns as lpcomp,
mutex_ns as mutex,
nfct_ns as nfct,
nvmc_ns as nvmc,
oscillators_ns as oscillators,
gpio_ns as gpio,
pdm_ns as pdm,
power_ns as power,
pwm_ns as pwm,
qdec_ns as qdec,
qspi_ns as qspi,
regulators_ns as regulators,
reset_ns as reset,
rtc_ns as rtc,
saadc_ns as saadc,
spim_ns as spim,
spis_ns as spis,
spu_s as spu,
tad_s as tad,
timer_ns as timer,
twim_ns as twim,
twis_ns as twis,
uarte_ns as uarte,
uicr_s as uicr,
usbd_ns as usbd,
usbregulator_ns as usbregulator,
vmc_ns as vmc,
wdt_ns as wdt,
};
/// Non-Secure mode (NS) peripherals
pub mod ns {
#[cfg(feature = "nrf5340-app-ns")]
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
COMP_NS as COMP,
CTRLAP_NS as CTRLAP,
DCNF_NS as DCNF,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S0_NS as I2S0,
IPC_NS as IPC,
KMU_NS as KMU,
LPCOMP_NS as LPCOMP,
MUTEX_NS as MUTEX,
NFCT_NS as NFCT,
NVMC_NS as NVMC,
OSCILLATORS_NS as OSCILLATORS,
P0_NS as P0,
P1_NS as P1,
PDM0_NS as PDM0,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
QDEC0_NS as QDEC0,
QDEC1_NS as QDEC1,
QSPI_NS as QSPI,
REGULATORS_NS as REGULATORS,
RESET_NS as RESET,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIM4_NS as SPIM4,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
USBD_NS as USBD,
USBREGULATOR_NS as USBREGULATOR,
VMC_NS as VMC,
WDT0_NS as WDT0,
WDT1_NS as WDT1,
};
}
/// Secure mode (S) peripherals
pub mod s {
#[cfg(feature = "nrf5340-app-s")]
#[doc(no_inline)]
pub use nrf_pac::{
CACHEDATA_S as CACHEDATA,
CACHEINFO_S as CACHEINFO,
CACHE_S as CACHE,
CLOCK_S as CLOCK,
COMP_S as COMP,
CRYPTOCELL_S as CRYPTOCELL,
CTI_S as CTI,
CTRLAP_S as CTRLAP,
DCNF_S as DCNF,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_S as FPU,
GPIOTE0_S as GPIOTE0,
I2S0_S as I2S0,
IPC_S as IPC,
KMU_S as KMU,
LPCOMP_S as LPCOMP,
MUTEX_S as MUTEX,
NFCT_S as NFCT,
NVMC_S as NVMC,
OSCILLATORS_S as OSCILLATORS,
P0_S as P0,
P1_S as P1,
PDM0_S as PDM0,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
QDEC0_S as QDEC0,
QDEC1_S as QDEC1,
QSPI_S as QSPI,
REGULATORS_S as REGULATORS,
RESET_S as RESET,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIM4_S as SPIM4,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
USBD_S as USBD,
USBREGULATOR_S as USBREGULATOR,
VMC_S as VMC,
WDT0_S as WDT0,
WDT1_S as WDT1,
};
}
pub use nrf_pac::*;
#[cfg(feature = "_ns")]
pub use ns::*;
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
COMP_NS as COMP,
CTRLAP_NS as CTRLAP,
DCNF_NS as DCNF,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S0_NS as I2S0,
IPC_NS as IPC,
KMU_NS as KMU,
LPCOMP_NS as LPCOMP,
MUTEX_NS as MUTEX,
NFCT_NS as NFCT,
NVMC_NS as NVMC,
OSCILLATORS_NS as OSCILLATORS,
P0_NS as P0,
P1_NS as P1,
PDM0_NS as PDM0,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
QDEC0_NS as QDEC0,
QDEC1_NS as QDEC1,
QSPI_NS as QSPI,
REGULATORS_NS as REGULATORS,
RESET_NS as RESET,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIM4_NS as SPIM4,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
USBD_NS as USBD,
USBREGULATOR_NS as USBREGULATOR,
VMC_NS as VMC,
WDT0_NS as WDT0,
WDT1_NS as WDT1,
};
#[cfg(feature = "_s")]
pub use s::*;
#[doc(no_inline)]
pub use nrf_pac::{
CACHEDATA_S as CACHEDATA,
CACHEINFO_S as CACHEINFO,
CACHE_S as CACHE,
CLOCK_S as CLOCK,
COMP_S as COMP,
CRYPTOCELL_S as CRYPTOCELL,
CTI_S as CTI,
CTRLAP_S as CTRLAP,
DCNF_S as DCNF,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_S as FPU,
GPIOTE0_S as GPIOTE0,
I2S0_S as I2S0,
IPC_S as IPC,
KMU_S as KMU,
LPCOMP_S as LPCOMP,
MUTEX_S as MUTEX,
NFCT_S as NFCT,
NVMC_S as NVMC,
OSCILLATORS_S as OSCILLATORS,
P0_S as P0,
P1_S as P1,
PDM0_S as PDM0,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
QDEC0_S as QDEC0,
QDEC1_S as QDEC1,
QSPI_S as QSPI,
REGULATORS_S as REGULATORS,
RESET_S as RESET,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIM4_S as SPIM4,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
USBD_S as USBD,
USBREGULATOR_S as USBREGULATOR,
VMC_S as VMC,
WDT0_S as WDT0,
WDT1_S as WDT1,
};
}
/// The maximum buffer size that the EasyDMA can send/recv in one operation.

48
embassy-nrf/src/chips/nrf5340_net.rs
View File

@ -2,55 +2,10 @@
#[allow(unused_imports)]
#[rustfmt::skip]
pub mod pac {
// The nRF5340 has a secure and non-secure (NS) mode.
// To avoid cfg spam, we remove _ns or _s suffixes here.
#[cfg(feature="rt")]
pub use nrf_pac::NVIC_PRIO_BITS;
pub use nrf_pac::{common, shared};
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf_pac::interrupt;
pub use nrf_pac::*;
#[doc(no_inline)]
pub use nrf_pac::{
Interrupt,
aar_ns as aar,
acl_ns as acl,
appmutex_ns as appmutex,
ccm_ns as ccm,
clock_ns as clock,
cti_ns as cti,
ctrlap_ns as ctrlap,
dcnf_ns as dcnf,
dppic_ns as dppic,
ecb_ns as ecb,
egu_ns as egu,
ficr_ns as ficr,
gpiote_ns as gpiote,
ipc_ns as ipc,
nvmc_ns as nvmc,
gpio_ns as gpio,
power_ns as power,
radio_ns as radio,
reset_ns as reset,
rng_ns as rng,
rtc_ns as rtc,
spim_ns as spim,
spis_ns as spis,
swi_ns as swi,
temp_ns as temp,
timer_ns as timer,
twim_ns as twim,
twis_ns as twis,
uarte_ns as uarte,
uicr_ns as uicr,
vmc_ns as vmc,
vreqctrl_ns as vreqctrl,
wdt_ns as wdt,
AAR_NS as AAR,
ACL_NS as ACL,
APPMUTEX_NS as APPMUTEX,
@ -93,7 +48,6 @@ pub mod pac {
VREQCTRL_NS as VREQCTRL,
WDT_NS as WDT,
};
}
/// The maximum buffer size that the EasyDMA can send/recv in one operation.

335
embassy-nrf/src/chips/nrf9120.rs
View File

@ -2,179 +2,124 @@
#[allow(unused_imports)]
#[rustfmt::skip]
pub mod pac {
// The nRF9120 has a secure and non-secure (NS) mode.
// To avoid cfg spam, we remove _ns or _s suffixes here.
#[cfg(feature="rt")]
pub use nrf_pac::NVIC_PRIO_BITS;
pub use nrf_pac::{common, shared};
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf_pac::interrupt;
#[doc(no_inline)]
pub use nrf_pac::{
Interrupt,
cc_host_rgf_s as cc_host_rgf,
clock_ns as clock,
cryptocell_s as cryptocell,
ctrl_ap_peri_s as ctrl_ap_peri,
dppic_ns as dppic,
egu_ns as egu,
ficr_s as ficr,
fpu_ns as fpu,
gpiote_s as gpiote,
i2s_ns as i2s,
ipc_ns as ipc,
kmu_ns as kmu,
nvmc_ns as nvmc,
gpio_ns as gpio,
pdm_ns as pdm,
power_ns as power,
pwm_ns as pwm,
regulators_ns as regulators,
rtc_ns as rtc,
saadc_ns as saadc,
spim_ns as spim,
spis_ns as spis,
spu_s as spu,
tad_s as tad,
timer_ns as timer,
twim_ns as twim,
twis_ns as twis,
uarte_ns as uarte,
uicr_s as uicr,
vmc_ns as vmc,
wdt_ns as wdt,
};
/// Non-Secure mode (NS) peripherals
pub mod ns {
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S_NS as I2S,
IPC_NS as IPC,
KMU_NS as KMU,
NVMC_NS as NVMC,
P0_NS as P0,
PDM_NS as PDM,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
REGULATORS_NS as REGULATORS,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
VMC_NS as VMC,
WDT_NS as WDT,
};
}
/// Secure mode (S) peripherals
pub mod s {
#[doc(no_inline)]
pub use nrf_pac::{
CC_HOST_RGF_S as CC_HOST_RGF,
CLOCK_S as CLOCK,
CRYPTOCELL_S as CRYPTOCELL,
CTRL_AP_PERI_S as CTRL_AP_PERI,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_NS as FPU,
GPIOTE0_S as GPIOTE0,
I2S_S as I2S,
IPC_S as IPC,
KMU_S as KMU,
NVMC_S as NVMC,
P0_S as P0,
PDM_S as PDM,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
REGULATORS_S as REGULATORS,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
VMC_S as VMC,
WDT_S as WDT,
};
}
pub use nrf_pac::*;
#[cfg(feature = "_ns")]
pub use ns::*;
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S_NS as I2S,
IPC_NS as IPC,
KMU_NS as KMU,
NVMC_NS as NVMC,
P0_NS as P0,
PDM_NS as PDM,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
REGULATORS_NS as REGULATORS,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
VMC_NS as VMC,
WDT_NS as WDT,
};
#[cfg(feature = "_s")]
pub use s::*;
#[doc(no_inline)]
pub use nrf_pac::{
CC_HOST_RGF_S as CC_HOST_RGF,
CLOCK_S as CLOCK,
CRYPTOCELL_S as CRYPTOCELL,
CTRL_AP_PERI_S as CTRL_AP_PERI,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_NS as FPU,
GPIOTE0_S as GPIOTE0,
I2S_S as I2S,
IPC_S as IPC,
KMU_S as KMU,
NVMC_S as NVMC,
P0_S as P0,
PDM_S as PDM,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
REGULATORS_S as REGULATORS,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
VMC_S as VMC,
WDT_S as WDT,
};
}
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
@ -295,30 +240,30 @@ embassy_hal_internal::peripherals! {
EGU5,
}
impl_uarte!(SERIAL0, UARTE0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
impl_uarte!(SERIAL1, UARTE1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
impl_uarte!(SERIAL2, UARTE2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
impl_uarte!(SERIAL3, UARTE3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
impl_uarte!(SERIAL1, UARTE1, SERIAL1);
impl_uarte!(SERIAL2, UARTE2, SERIAL2);
impl_uarte!(SERIAL3, UARTE3, SERIAL3);
impl_spim!(SERIAL0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
impl_spim!(SERIAL1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
impl_spim!(SERIAL2, SPIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
impl_spim!(SERIAL3, SPIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
impl_spim!(SERIAL0, SPIM0, SERIAL0);
impl_spim!(SERIAL1, SPIM1, SERIAL1);
impl_spim!(SERIAL2, SPIM2, SERIAL2);
impl_spim!(SERIAL3, SPIM3, SERIAL3);
impl_spis!(SERIAL0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
impl_spis!(SERIAL1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
impl_spis!(SERIAL2, SPIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
impl_spis!(SERIAL3, SPIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
impl_spis!(SERIAL0, SPIS0, SERIAL0);
impl_spis!(SERIAL1, SPIS1, SERIAL1);
impl_spis!(SERIAL2, SPIS2, SERIAL2);
impl_spis!(SERIAL3, SPIS3, SERIAL3);
impl_twim!(SERIAL0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
impl_twim!(SERIAL1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
impl_twim!(SERIAL2, TWIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
impl_twim!(SERIAL3, TWIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
impl_twim!(SERIAL0, TWIM0, SERIAL0);
impl_twim!(SERIAL1, TWIM1, SERIAL1);
impl_twim!(SERIAL2, TWIM2, SERIAL2);
impl_twim!(SERIAL3, TWIM3, SERIAL3);
impl_twis!(SERIAL0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
impl_twis!(SERIAL1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
impl_twis!(SERIAL2, TWIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
impl_twis!(SERIAL3, TWIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
impl_twis!(SERIAL0, TWIS0, SERIAL0);
impl_twis!(SERIAL1, TWIS1, SERIAL1);
impl_twis!(SERIAL2, TWIS2, SERIAL2);
impl_twis!(SERIAL3, TWIS3, SERIAL3);
impl_pwm!(PWM0, PWM0, PWM0);
impl_pwm!(PWM1, PWM1, PWM1);
@ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5);
embassy_hal_internal::interrupt_mod!(
SPU,
CLOCK_POWER,
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0,
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1,
SPIM2_SPIS2_TWIM2_TWIS2_UARTE2,
SPIM3_SPIS3_TWIM3_TWIS3_UARTE3,
SERIAL0,
SERIAL1,
SERIAL2,
SERIAL3,
GPIOTE0,
SAADC,
TIMER0,
@ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!(
PWM0,
PWM1,
PWM2,
PDM,
PWM3,
PDM,
I2S,
IPC,
FPU,

335
embassy-nrf/src/chips/nrf9160.rs
View File

@ -2,179 +2,124 @@
#[allow(unused_imports)]
#[rustfmt::skip]
pub mod pac {
// The nRF9160 has a secure and non-secure (NS) mode.
// To avoid cfg spam, we remove _ns or _s suffixes here.
#[cfg(feature="rt")]
pub use nrf_pac::NVIC_PRIO_BITS;
pub use nrf_pac::{common, shared};
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf_pac::interrupt;
#[doc(no_inline)]
pub use nrf_pac::{
Interrupt,
cc_host_rgf_s as cc_host_rgf,
clock_ns as clock,
cryptocell_s as cryptocell,
ctrl_ap_peri_s as ctrl_ap_peri,
dppic_ns as dppic,
egu_ns as egu,
ficr_s as ficr,
fpu_ns as fpu,
gpiote_s as gpiote,
i2s_ns as i2s,
ipc_ns as ipc,
kmu_ns as kmu,
nvmc_ns as nvmc,
gpio_ns as gpio,
pdm_ns as pdm,
power_ns as power,
pwm_ns as pwm,
regulators_ns as regulators,
rtc_ns as rtc,
saadc_ns as saadc,
spim_ns as spim,
spis_ns as spis,
spu_s as spu,
tad_s as tad,
timer_ns as timer,
twim_ns as twim,
twis_ns as twis,
uarte_ns as uarte,
uicr_s as uicr,
vmc_ns as vmc,
wdt_ns as wdt,
};
/// Non-Secure mode (NS) peripherals
pub mod ns {
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S_NS as I2S,
IPC_NS as IPC,
KMU_NS as KMU,
NVMC_NS as NVMC,
P0_NS as P0,
PDM_NS as PDM,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
REGULATORS_NS as REGULATORS,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
VMC_NS as VMC,
WDT_NS as WDT,
};
}
/// Secure mode (S) peripherals
pub mod s {
#[doc(no_inline)]
pub use nrf_pac::{
CC_HOST_RGF_S as CC_HOST_RGF,
CLOCK_S as CLOCK,
CRYPTOCELL_S as CRYPTOCELL,
CTRL_AP_PERI_S as CTRL_AP_PERI,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_S as FPU,
GPIOTE0_S as GPIOTE0,
I2S_S as I2S,
IPC_S as IPC,
KMU_S as KMU,
NVMC_S as NVMC,
P0_S as P0,
PDM_S as PDM,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
REGULATORS_S as REGULATORS,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
VMC_S as VMC,
WDT_S as WDT,
};
}
pub use nrf_pac::*;
#[cfg(feature = "_ns")]
pub use ns::*;
#[doc(no_inline)]
pub use nrf_pac::{
CLOCK_NS as CLOCK,
DPPIC_NS as DPPIC,
EGU0_NS as EGU0,
EGU1_NS as EGU1,
EGU2_NS as EGU2,
EGU3_NS as EGU3,
EGU4_NS as EGU4,
EGU5_NS as EGU5,
FPU_NS as FPU,
GPIOTE1_NS as GPIOTE1,
I2S_NS as I2S,
IPC_NS as IPC,
KMU_NS as KMU,
NVMC_NS as NVMC,
P0_NS as P0,
PDM_NS as PDM,
POWER_NS as POWER,
PWM0_NS as PWM0,
PWM1_NS as PWM1,
PWM2_NS as PWM2,
PWM3_NS as PWM3,
REGULATORS_NS as REGULATORS,
RTC0_NS as RTC0,
RTC1_NS as RTC1,
SAADC_NS as SAADC,
SPIM0_NS as SPIM0,
SPIM1_NS as SPIM1,
SPIM2_NS as SPIM2,
SPIM3_NS as SPIM3,
SPIS0_NS as SPIS0,
SPIS1_NS as SPIS1,
SPIS2_NS as SPIS2,
SPIS3_NS as SPIS3,
TIMER0_NS as TIMER0,
TIMER1_NS as TIMER1,
TIMER2_NS as TIMER2,
TWIM0_NS as TWIM0,
TWIM1_NS as TWIM1,
TWIM2_NS as TWIM2,
TWIM3_NS as TWIM3,
TWIS0_NS as TWIS0,
TWIS1_NS as TWIS1,
TWIS2_NS as TWIS2,
TWIS3_NS as TWIS3,
UARTE0_NS as UARTE0,
UARTE1_NS as UARTE1,
UARTE2_NS as UARTE2,
UARTE3_NS as UARTE3,
VMC_NS as VMC,
WDT_NS as WDT,
};
#[cfg(feature = "_s")]
pub use s::*;
#[doc(no_inline)]
pub use nrf_pac::{
CC_HOST_RGF_S as CC_HOST_RGF,
CLOCK_S as CLOCK,
CRYPTOCELL_S as CRYPTOCELL,
CTRL_AP_PERI_S as CTRL_AP_PERI,
DPPIC_S as DPPIC,
EGU0_S as EGU0,
EGU1_S as EGU1,
EGU2_S as EGU2,
EGU3_S as EGU3,
EGU4_S as EGU4,
EGU5_S as EGU5,
FICR_S as FICR,
FPU_S as FPU,
GPIOTE0_S as GPIOTE0,
I2S_S as I2S,
IPC_S as IPC,
KMU_S as KMU,
NVMC_S as NVMC,
P0_S as P0,
PDM_S as PDM,
POWER_S as POWER,
PWM0_S as PWM0,
PWM1_S as PWM1,
PWM2_S as PWM2,
PWM3_S as PWM3,
REGULATORS_S as REGULATORS,
RTC0_S as RTC0,
RTC1_S as RTC1,
SAADC_S as SAADC,
SPIM0_S as SPIM0,
SPIM1_S as SPIM1,
SPIM2_S as SPIM2,
SPIM3_S as SPIM3,
SPIS0_S as SPIS0,
SPIS1_S as SPIS1,
SPIS2_S as SPIS2,
SPIS3_S as SPIS3,
SPU_S as SPU,
TAD_S as TAD,
TIMER0_S as TIMER0,
TIMER1_S as TIMER1,
TIMER2_S as TIMER2,
TWIM0_S as TWIM0,
TWIM1_S as TWIM1,
TWIM2_S as TWIM2,
TWIM3_S as TWIM3,
TWIS0_S as TWIS0,
TWIS1_S as TWIS1,
TWIS2_S as TWIS2,
TWIS3_S as TWIS3,
UARTE0_S as UARTE0,
UARTE1_S as UARTE1,
UARTE2_S as UARTE2,
UARTE3_S as UARTE3,
UICR_S as UICR,
VMC_S as VMC,
WDT_S as WDT,
};
}
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
@ -295,30 +240,30 @@ embassy_hal_internal::peripherals! {
EGU5,
}
impl_uarte!(SERIAL0, UARTE0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
impl_uarte!(SERIAL1, UARTE1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
impl_uarte!(SERIAL2, UARTE2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
impl_uarte!(SERIAL3, UARTE3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
impl_uarte!(SERIAL1, UARTE1, SERIAL1);
impl_uarte!(SERIAL2, UARTE2, SERIAL2);
impl_uarte!(SERIAL3, UARTE3, SERIAL3);
impl_spim!(SERIAL0, SPIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
impl_spim!(SERIAL1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
impl_spim!(SERIAL2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
impl_spim!(SERIAL3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
impl_spim!(SERIAL0, SPIM0, SERIAL0);
impl_spim!(SERIAL1, SPIM1, SERIAL1);
impl_spim!(SERIAL2, SPIM2, SERIAL2);
impl_spim!(SERIAL3, SPIM3, SERIAL3);
impl_spis!(SERIAL0, SPIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
impl_spis!(SERIAL1, SPIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
impl_spis!(SERIAL2, SPIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
impl_spis!(SERIAL3, SPIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
impl_spis!(SERIAL0, SPIS0, SERIAL0);
impl_spis!(SERIAL1, SPIS1, SERIAL1);
impl_spis!(SERIAL2, SPIS2, SERIAL2);
impl_spis!(SERIAL3, SPIS3, SERIAL3);
impl_twim!(SERIAL0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
impl_twim!(SERIAL1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
impl_twim!(SERIAL2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
impl_twim!(SERIAL3, TWIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
impl_twim!(SERIAL0, TWIM0, SERIAL0);
impl_twim!(SERIAL1, TWIM1, SERIAL1);
impl_twim!(SERIAL2, TWIM2, SERIAL2);
impl_twim!(SERIAL3, TWIM3, SERIAL3);
impl_twis!(SERIAL0, TWIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
impl_twis!(SERIAL1, TWIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
impl_twis!(SERIAL2, TWIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
impl_twis!(SERIAL3, TWIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
impl_twis!(SERIAL0, TWIS0, SERIAL0);
impl_twis!(SERIAL1, TWIS1, SERIAL1);
impl_twis!(SERIAL2, TWIS2, SERIAL2);
impl_twis!(SERIAL3, TWIS3, SERIAL3);
impl_pwm!(PWM0, PWM0, PWM0);
impl_pwm!(PWM1, PWM1, PWM1);
@ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5);
embassy_hal_internal::interrupt_mod!(
SPU,
CLOCK_POWER,
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0,
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1,
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2,
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3,
SERIAL0,
SERIAL1,
SERIAL2,
SERIAL3,
GPIOTE0,
SAADC,
TIMER0,
@ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!(
PWM0,
PWM1,
PWM2,
PDM,
PWM3,
PDM,
I2S,
IPC,
FPU,

2
embassy-nrf/src/lib.rs
View File

@ -170,7 +170,7 @@ mod chip;
///
/// bind_interrupts!(struct Irqs {
/// SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
/// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>;
/// TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
/// });
/// ```

2
embassy-nrf/src/time_driver.rs
View File

@ -132,7 +132,7 @@ impl RtcDriver {
r.intenset().write(|w| {
w.set_ovrflw(true);
w.set_compare3(true);
w.set_compare(3, true);
});
r.tasks_clear().write_value(1);

4
embassy-nrf/src/usb/vbus_detect.rs
View File

@ -29,14 +29,14 @@ pub trait VbusDetect {
}
#[cfg(not(feature = "_nrf5340"))]
type UsbRegIrq = interrupt::typelevel::POWER_CLOCK;
type UsbRegIrq = interrupt::typelevel::CLOCK_POWER;
#[cfg(feature = "_nrf5340")]
type UsbRegIrq = interrupt::typelevel::USBREGULATOR;
#[cfg(not(feature = "_nrf5340"))]
const USB_REG_PERI: pac::power::Power = pac::POWER;
#[cfg(feature = "_nrf5340")]
const USB_REG_PERI: pac::usbregulator::Usbregulator = pac::USBREGULATOR;
const USB_REG_PERI: pac::usbreg::Usbreg = pac::USBREGULATOR;
/// Interrupt handler.
pub struct InterruptHandler {

2
examples/nrf52840-rtic/src/bin/blinky.rs
View File

@ -4,7 +4,7 @@
use {defmt_rtt as _, panic_probe as _};
#[rtic::app(device = embassy_nrf, peripherals = false, dispatchers = [SWI0_EGU0, SWI1_EGU1])]
#[rtic::app(device = embassy_nrf, peripherals = false, dispatchers = [EGU0_SWI0, EGU1_SWI1])]
mod app {
use defmt::info;
use embassy_nrf::gpio::{Level, Output, OutputDrive};

2
examples/nrf52840/src/bin/buffered_uart.rs
View File

@ -9,7 +9,7 @@ use embedded_io_async::Write;
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
});
#[embassy_executor::main]

16
examples/nrf52840/src/bin/multiprio.rs
View File

@ -112,12 +112,12 @@ static EXECUTOR_MED: InterruptExecutor = InterruptExecutor::new();
static EXECUTOR_LOW: StaticCell<Executor> = StaticCell::new();
#[interrupt]
unsafe fn SWI1_EGU1() {
unsafe fn EGU1_SWI1() {
EXECUTOR_HIGH.on_interrupt()
}
#[interrupt]
unsafe fn SWI0_EGU0() {
unsafe fn EGU0_SWI0() {
EXECUTOR_MED.on_interrupt()
}
@ -127,14 +127,14 @@ fn main() -> ! {
let _p = embassy_nrf::init(Default::default());
// High-priority executor: SWI1_EGU1, priority level 6
interrupt::SWI1_EGU1.set_priority(Priority::P6);
let spawner = EXECUTOR_HIGH.start(interrupt::SWI1_EGU1);
// High-priority executor: EGU1_SWI1, priority level 6
interrupt::EGU1_SWI1.set_priority(Priority::P6);
let spawner = EXECUTOR_HIGH.start(interrupt::EGU1_SWI1);
unwrap!(spawner.spawn(run_high()));
// Medium-priority executor: SWI0_EGU0, priority level 7
interrupt::SWI0_EGU0.set_priority(Priority::P7);
let spawner = EXECUTOR_MED.start(interrupt::SWI0_EGU0);
// Medium-priority executor: EGU0_SWI0, priority level 7
interrupt::EGU0_SWI0.set_priority(Priority::P7);
let spawner = EXECUTOR_MED.start(interrupt::EGU0_SWI0);
unwrap!(spawner.spawn(run_med()));
// Low priority executor: runs in thread mode, using WFE/SEV

2
examples/nrf52840/src/bin/spis.rs
View File

@ -8,7 +8,7 @@ use embassy_nrf::{bind_interrupts, peripherals, spis};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
SPIM2_SPIS2_SPI2 => spis::InterruptHandler<peripherals::SPI2>;
SPI2 => spis::InterruptHandler<peripherals::SPI2>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/twim.rs
View File

@ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _};
const ADDRESS: u8 = 0x50;
bind_interrupts!(struct Irqs {
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>;
TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/twim_lowpower.rs
View File

@ -19,7 +19,7 @@ use {defmt_rtt as _, panic_probe as _};
const ADDRESS: u8 = 0x50;
bind_interrupts!(struct Irqs {
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>;
TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/twis.rs
View File

@ -10,7 +10,7 @@ use embassy_nrf::{bind_interrupts, peripherals};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twis::InterruptHandler<peripherals::TWISPI0>;
TWISPI0 => twis::InterruptHandler<peripherals::TWISPI0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/uart.rs
View File

@ -7,7 +7,7 @@ use embassy_nrf::{bind_interrupts, peripherals, uarte};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;
UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/uart_idle.rs
View File

@ -8,7 +8,7 @@ use embassy_nrf::{bind_interrupts, uarte};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
UARTE0_UART0 => uarte::InterruptHandler<UARTE0>;
UARTE0 => uarte::InterruptHandler<UARTE0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/uart_split.rs
View File

@ -13,7 +13,7 @@ use {defmt_rtt as _, panic_probe as _};
static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new();
bind_interrupts!(struct Irqs {
UARTE0_UART0 => uarte::InterruptHandler<UARTE0>;
UARTE0 => uarte::InterruptHandler<UARTE0>;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/usb_ethernet.rs
View File

@ -18,7 +18,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
RNG => rng::InterruptHandler<peripherals::RNG>;
});

2
examples/nrf52840/src/bin/usb_hid_keyboard.rs
View File

@ -21,7 +21,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
});
static SUSPENDED: AtomicBool = AtomicBool::new(false);

2
examples/nrf52840/src/bin/usb_hid_mouse.rs
View File

@ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/usb_serial.rs
View File

@ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
});
#[embassy_executor::main]

2
examples/nrf52840/src/bin/usb_serial_multitask.rs
View File

@ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
});
type MyDriver = Driver<'static, peripherals::USBD, HardwareVbusDetect>;

2
examples/nrf52840/src/bin/usb_serial_winusb.rs
View File

@ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
USBD => usb::InterruptHandler<peripherals::USBD>;
POWER_CLOCK => usb::vbus_detect::InterruptHandler;
CLOCK_POWER => usb::vbus_detect::InterruptHandler;
});
// This is a randomly generated GUID to allow clients on Windows to find our device

2
examples/nrf9151/ns/src/bin/uart.rs
View File

@ -7,7 +7,7 @@ use embassy_nrf::{bind_interrupts, peripherals, uarte};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 => uarte::InterruptHandler<peripherals::SERIAL0>;
SERIAL0 => uarte::InterruptHandler<peripherals::SERIAL0>;
});
#[embassy_executor::main]

2
examples/nrf9160/src/bin/modem_tcp_client.rs
View File

@ -28,7 +28,7 @@ fn IPC() {
}
bind_interrupts!(struct Irqs {
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;
SERIAL0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;
});
#[embassy_executor::task]

28
tests/nrf/src/common.rs
View File

@ -55,9 +55,9 @@ define_peris!(
PIN_X = P0_13,
UART0 = UARTE0,
SPIM0 = TWISPI0,
@irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
@irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
);
#[cfg(feature = "nrf52833")]
@ -67,11 +67,11 @@ define_peris!(
UART0 = UARTE0,
UART1 = UARTE1,
SPIM0 = TWISPI0,
@irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;},
@irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;},
@irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
@irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
);
#[cfg(feature = "nrf52840")]
@ -81,11 +81,11 @@ define_peris!(
UART0 = UARTE0,
UART1 = UARTE1,
SPIM0 = TWISPI0,
@irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;},
@irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;},
@irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;},
@irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
@irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;},
);
#[cfg(feature = "nrf5340")]
@ -109,9 +109,9 @@ define_peris!(
UART0 = SERIAL0,
UART1 = SERIAL1,
SPIM0 = SERIAL0,
@irq UART0 = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => uarte::InterruptHandler<peripherals::SERIAL0>;},
@irq UART1 = {UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 => uarte::InterruptHandler<peripherals::SERIAL1>;},
@irq UART0_BUFFERED = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;},
@irq UART1_BUFFERED = {UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 => buffered_uarte::InterruptHandler<peripherals::SERIAL1>;},
@irq SPIM0 = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => spim::InterruptHandler<peripherals::SERIAL0>;},
@irq UART0 = {SERIAL0 => uarte::InterruptHandler<peripherals::SERIAL0>;},
@irq UART1 = {SERIAL1 => uarte::InterruptHandler<peripherals::SERIAL1>;},
@irq UART0_BUFFERED = {SERIAL0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;},
@irq UART1_BUFFERED = {SERIAL1 => buffered_uarte::InterruptHandler<peripherals::SERIAL1>;},
@irq SPIM0 = {SERIAL0 => spim::InterruptHandler<peripherals::SERIAL0>;},
);