mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 06:42:32 +00:00
remove dev files
This commit is contained in:
Bruno Bousquet
parent
50039b17a7
commit
69badfb845
33
examples/stm32f1/.vscode/launch.json
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33
examples/stm32f1/.vscode/launch.json
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@ -1,33 +0,0 @@
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{
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/*
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* Requires the Rust Language Server (rust-analyzer) and Cortex-Debug extensions
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* https://marketplace.visualstudio.com/items?itemName=rust-lang.rust-analyzer
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* https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
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*/
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"version": "0.2.0",
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"configurations": [
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{
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/* Configuration for the STM32F446 Discovery board */
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"type": "cortex-debug",
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"request": "launch",
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"name": "Debug (OpenOCD)",
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"servertype": "openocd",
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"cwd": "${workspaceRoot}",
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"preLaunchTask": "Cargo Build (debug)",
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"runToEntryPoint": "main",
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"executable": "./target/thumbv7m-none-eabi/debug/pwm_input",
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/* Run `cargo build --example itm` and uncomment this line to run itm example */
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// "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
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"device": "STM32F103T8",
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"configFiles": [
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"interface/stlink.cfg",
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"target/stm32f1x.cfg"
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],
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"postLaunchCommands": [
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"monitor arm semihosting enable"
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],
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"postRestartCommands": [],
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"postResetCommands": [],
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}
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]
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}
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21
examples/stm32f1/.vscode/tasks.json
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21
examples/stm32f1/.vscode/tasks.json
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{
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"version": "2.0.0",
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"tasks": [
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{
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"type": "cargo",
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"command": "build",
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"problemMatcher": [
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"$rustc"
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],
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"args": [
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"--bin",
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"pwm_input"
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],
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"group": {
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"kind": "build",
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"isDefault": true
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},
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"label": "Cargo Build (debug)",
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}
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]
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}
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@ -1,5 +0,0 @@
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# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
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source [find interface/stlink.cfg]
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source [find target/stm32f1x.cfg]
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@ -1,40 +0,0 @@
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target extended-remote :3333
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# print demangled symbols
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set print asm-demangle on
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# set backtrace limit to not have infinite backtrace loops
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set backtrace limit 32
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# detect unhandled exceptions, hard faults and panics
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break DefaultHandler
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break HardFault
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break rust_begin_unwind
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# # run the next few lines so the panic message is printed immediately
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# # the number needs to be adjusted for your panic handler
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# commands $bpnum
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# next 4
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# end
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# *try* to stop at the user entry point (it might be gone due to inlining)
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break main
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monitor arm semihosting enable
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# # send captured ITM to the file itm.fifo
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# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
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# # 8000000 must match the core clock frequency
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# monitor tpiu config internal itm.txt uart off 8000000
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
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# # 8000000 must match the core clock frequency
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# # 2000000 is the frequency of the SWO pin
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# monitor tpiu config external uart off 8000000 2000000
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# # enable ITM port 0
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# monitor itm port 0 on
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load
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# start the process but immediately halt the processor
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stepi
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@ -1,11 +1,9 @@
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
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# runner = "probe-rs run --chip STM32F429ZITx"
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runner = "arm-none-eabi-gdb -q -x openocd.gdb"
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runner = "probe-rs run --chip STM32F429ZITx"
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[build]
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# target = "thumbv7em-none-eabi"
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target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
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target = "thumbv7em-none-eabi"
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[env]
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DEFMT_LOG = "trace"
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33
examples/stm32f4/.vscode/launch.json
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33
examples/stm32f4/.vscode/launch.json
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@ -1,33 +0,0 @@
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{
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/*
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* Requires the Rust Language Server (rust-analyzer) and Cortex-Debug extensions
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* https://marketplace.visualstudio.com/items?itemName=rust-lang.rust-analyzer
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* https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
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*/
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"version": "0.2.0",
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"configurations": [
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{
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/* Configuration for the STM32F446 Discovery board */
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"type": "cortex-debug",
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"request": "launch",
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"name": "Debug (OpenOCD)",
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"servertype": "openocd",
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"cwd": "${workspaceRoot}",
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"preLaunchTask": "Cargo Build (debug)",
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"runToEntryPoint": "main",
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"executable": "./target/thumbv7em-none-eabihf/debug/pwm_input",
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/* Run `cargo build --example itm` and uncomment this line to run itm example */
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// "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
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"device": "STM32F446RET6",
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"configFiles": [
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"interface/stlink.cfg",
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"target/stm32f4x.cfg"
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],
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"postLaunchCommands": [
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"monitor arm semihosting enable"
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],
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"postRestartCommands": [],
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"postResetCommands": [],
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}
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]
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}
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21
examples/stm32f4/.vscode/tasks.json
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21
examples/stm32f4/.vscode/tasks.json
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@ -1,21 +0,0 @@
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{
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"version": "2.0.0",
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"tasks": [
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{
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"type": "cargo",
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"command": "build",
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"problemMatcher": [
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"$rustc"
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],
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"args": [
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"--bin",
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"pwm_input"
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],
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"group": {
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"kind": "build",
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"isDefault": true
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},
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"label": "Cargo Build (debug)",
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}
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]
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}
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@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
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[dependencies]
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# Change stm32f429zi to your chip name, if necessary.
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f446re", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] }
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f429zi", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] }
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embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
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embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
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embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
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@ -1,5 +0,0 @@
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# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
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source [find interface/stlink.cfg]
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source [find target/stm32f4x.cfg]
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@ -1,40 +0,0 @@
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target extended-remote :3333
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# print demangled symbols
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set print asm-demangle on
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# set backtrace limit to not have infinite backtrace loops
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set backtrace limit 32
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# detect unhandled exceptions, hard faults and panics
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break DefaultHandler
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break HardFault
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break rust_begin_unwind
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# # run the next few lines so the panic message is printed immediately
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# # the number needs to be adjusted for your panic handler
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# commands $bpnum
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# next 4
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# end
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# *try* to stop at the user entry point (it might be gone due to inlining)
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break main
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monitor arm semihosting enable
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# # send captured ITM to the file itm.fifo
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# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
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# # 8000000 must match the core clock frequency
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# monitor tpiu config internal itm.txt uart off 8000000
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
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# # 8000000 must match the core clock frequency
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# # 2000000 is the frequency of the SWO pin
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# monitor tpiu config external uart off 8000000 2000000
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# # enable ITM port 0
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# monitor itm port 0 on
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load
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# start the process but immediately halt the processor
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stepi
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@ -1,5 +1,5 @@
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[toolchain]
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channel = "1.77"
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channel = "1.78"
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components = [ "rust-src", "rustfmt", "llvm-tools" ]
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targets = [
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"thumbv7em-none-eabi",
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