diff --git a/examples/stm32f1/.vscode/launch.json b/examples/stm32f1/.vscode/launch.json deleted file mode 100644 index 71f203614..000000000 --- a/examples/stm32f1/.vscode/launch.json +++ /dev/null @@ -1,33 +0,0 @@ -{ - /* - * Requires the Rust Language Server (rust-analyzer) and Cortex-Debug extensions - * https://marketplace.visualstudio.com/items?itemName=rust-lang.rust-analyzer - * https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug - */ - "version": "0.2.0", - "configurations": [ - { - /* Configuration for the STM32F446 Discovery board */ - "type": "cortex-debug", - "request": "launch", - "name": "Debug (OpenOCD)", - "servertype": "openocd", - "cwd": "${workspaceRoot}", - "preLaunchTask": "Cargo Build (debug)", - "runToEntryPoint": "main", - "executable": "./target/thumbv7m-none-eabi/debug/pwm_input", - /* Run `cargo build --example itm` and uncomment this line to run itm example */ - // "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm", - "device": "STM32F103T8", - "configFiles": [ - "interface/stlink.cfg", - "target/stm32f1x.cfg" - ], - "postLaunchCommands": [ - "monitor arm semihosting enable" - ], - "postRestartCommands": [], - "postResetCommands": [], - } - ] -} \ No newline at end of file diff --git a/examples/stm32f1/.vscode/tasks.json b/examples/stm32f1/.vscode/tasks.json deleted file mode 100644 index de7013b12..000000000 --- a/examples/stm32f1/.vscode/tasks.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "version": "2.0.0", - "tasks": [ - { - "type": "cargo", - "command": "build", - "problemMatcher": [ - "$rustc" - ], - "args": [ - "--bin", - "pwm_input" - ], - "group": { - "kind": "build", - "isDefault": true - }, - "label": "Cargo Build (debug)", - } - ] -} \ No newline at end of file diff --git a/examples/stm32f1/openocd.cfg b/examples/stm32f1/openocd.cfg deleted file mode 100644 index 0325cd651..000000000 --- a/examples/stm32f1/openocd.cfg +++ /dev/null @@ -1,5 +0,0 @@ -# Sample OpenOCD configuration for the STM32F3DISCOVERY development board - -source [find interface/stlink.cfg] - -source [find target/stm32f1x.cfg] diff --git a/examples/stm32f1/openocd.gdb b/examples/stm32f1/openocd.gdb deleted file mode 100644 index 7795319fb..000000000 --- a/examples/stm32f1/openocd.gdb +++ /dev/null @@ -1,40 +0,0 @@ -target extended-remote :3333 - -# print demangled symbols -set print asm-demangle on - -# set backtrace limit to not have infinite backtrace loops -set backtrace limit 32 - -# detect unhandled exceptions, hard faults and panics -break DefaultHandler -break HardFault -break rust_begin_unwind -# # run the next few lines so the panic message is printed immediately -# # the number needs to be adjusted for your panic handler -# commands $bpnum -# next 4 -# end - -# *try* to stop at the user entry point (it might be gone due to inlining) -break main - -monitor arm semihosting enable - -# # send captured ITM to the file itm.fifo -# # (the microcontroller SWO pin must be connected to the programmer SWO pin) -# # 8000000 must match the core clock frequency -# monitor tpiu config internal itm.txt uart off 8000000 - -# # OR: make the microcontroller SWO pin output compatible with UART (8N1) -# # 8000000 must match the core clock frequency -# # 2000000 is the frequency of the SWO pin -# monitor tpiu config external uart off 8000000 2000000 - -# # enable ITM port 0 -# monitor itm port 0 on - -load - -# start the process but immediately halt the processor -stepi diff --git a/examples/stm32f4/.cargo/config.toml b/examples/stm32f4/.cargo/config.toml index f5a4af51a..16efa8e6f 100644 --- a/examples/stm32f4/.cargo/config.toml +++ b/examples/stm32f4/.cargo/config.toml @@ -1,11 +1,9 @@ [target.'cfg(all(target_arch = "arm", target_os = "none"))'] # replace STM32F429ZITx with your chip as listed in `probe-rs chip list` -# runner = "probe-rs run --chip STM32F429ZITx" -runner = "arm-none-eabi-gdb -q -x openocd.gdb" +runner = "probe-rs run --chip STM32F429ZITx" [build] -# target = "thumbv7em-none-eabi" -target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +target = "thumbv7em-none-eabi" [env] DEFMT_LOG = "trace" diff --git a/examples/stm32f4/.vscode/launch.json b/examples/stm32f4/.vscode/launch.json deleted file mode 100644 index a9849e0da..000000000 --- a/examples/stm32f4/.vscode/launch.json +++ /dev/null @@ -1,33 +0,0 @@ -{ - /* - * Requires the Rust Language Server (rust-analyzer) and Cortex-Debug extensions - * https://marketplace.visualstudio.com/items?itemName=rust-lang.rust-analyzer - * https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug - */ - "version": "0.2.0", - "configurations": [ - { - /* Configuration for the STM32F446 Discovery board */ - "type": "cortex-debug", - "request": "launch", - "name": "Debug (OpenOCD)", - "servertype": "openocd", - "cwd": "${workspaceRoot}", - "preLaunchTask": "Cargo Build (debug)", - "runToEntryPoint": "main", - "executable": "./target/thumbv7em-none-eabihf/debug/pwm_input", - /* Run `cargo build --example itm` and uncomment this line to run itm example */ - // "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm", - "device": "STM32F446RET6", - "configFiles": [ - "interface/stlink.cfg", - "target/stm32f4x.cfg" - ], - "postLaunchCommands": [ - "monitor arm semihosting enable" - ], - "postRestartCommands": [], - "postResetCommands": [], - } - ] -} \ No newline at end of file diff --git a/examples/stm32f4/.vscode/tasks.json b/examples/stm32f4/.vscode/tasks.json deleted file mode 100644 index de7013b12..000000000 --- a/examples/stm32f4/.vscode/tasks.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "version": "2.0.0", - "tasks": [ - { - "type": "cargo", - "command": "build", - "problemMatcher": [ - "$rustc" - ], - "args": [ - "--bin", - "pwm_input" - ], - "group": { - "kind": "build", - "isDefault": true - }, - "label": "Cargo Build (debug)", - } - ] -} \ No newline at end of file diff --git a/examples/stm32f4/Cargo.toml b/examples/stm32f4/Cargo.toml index ee7594c95..1eb1ae6db 100644 --- a/examples/stm32f4/Cargo.toml +++ b/examples/stm32f4/Cargo.toml @@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0" [dependencies] # Change stm32f429zi to your chip name, if necessary. -embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f446re", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] } +embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f429zi", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] } embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] } embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] } embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] } diff --git a/examples/stm32f4/openocd.cfg b/examples/stm32f4/openocd.cfg deleted file mode 100644 index e41d52b1a..000000000 --- a/examples/stm32f4/openocd.cfg +++ /dev/null @@ -1,5 +0,0 @@ -# Sample OpenOCD configuration for the STM32F3DISCOVERY development board - -source [find interface/stlink.cfg] - -source [find target/stm32f4x.cfg] diff --git a/examples/stm32f4/openocd.gdb b/examples/stm32f4/openocd.gdb deleted file mode 100644 index 7795319fb..000000000 --- a/examples/stm32f4/openocd.gdb +++ /dev/null @@ -1,40 +0,0 @@ -target extended-remote :3333 - -# print demangled symbols -set print asm-demangle on - -# set backtrace limit to not have infinite backtrace loops -set backtrace limit 32 - -# detect unhandled exceptions, hard faults and panics -break DefaultHandler -break HardFault -break rust_begin_unwind -# # run the next few lines so the panic message is printed immediately -# # the number needs to be adjusted for your panic handler -# commands $bpnum -# next 4 -# end - -# *try* to stop at the user entry point (it might be gone due to inlining) -break main - -monitor arm semihosting enable - -# # send captured ITM to the file itm.fifo -# # (the microcontroller SWO pin must be connected to the programmer SWO pin) -# # 8000000 must match the core clock frequency -# monitor tpiu config internal itm.txt uart off 8000000 - -# # OR: make the microcontroller SWO pin output compatible with UART (8N1) -# # 8000000 must match the core clock frequency -# # 2000000 is the frequency of the SWO pin -# monitor tpiu config external uart off 8000000 2000000 - -# # enable ITM port 0 -# monitor itm port 0 on - -load - -# start the process but immediately halt the processor -stepi diff --git a/rust-toolchain.toml b/rust-toolchain.toml index 2f5d17069..57185e217 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -1,5 +1,5 @@ [toolchain] -channel = "1.77" +channel = "1.78" components = [ "rust-src", "rustfmt", "llvm-tools" ] targets = [ "thumbv7em-none-eabi",