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Add docs to RP2040 PWM
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@ -10,16 +10,40 @@ use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::{pac, peripherals, RegExt};
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use crate::{pac, peripherals, RegExt};
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/// The configuration of a PWM slice.
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///Note the period in clock cycles of a slice can be computed as:
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/// (top + 1) * (phase_correct ? 1 : 2) * divider
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#[non_exhaustive]
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#[non_exhaustive]
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#[derive(Clone)]
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#[derive(Clone)]
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pub struct Config {
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pub struct Config {
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/// Inverts the PWM output signal on channel A.
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pub invert_a: bool,
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pub invert_a: bool,
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/// Inverts the PWM output signal on channel B.
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pub invert_b: bool,
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pub invert_b: bool,
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/// Enables phase-correct mode for PWM operation.
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/// In phase-correct mode, the PWM signal is generated in such a way that
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/// the pulse is always centered regardless of the duty cycle.
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/// The output frequency is halved when phase-correct mode is enabled.
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pub phase_correct: bool,
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pub phase_correct: bool,
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/// Enables the PWM slice, allowing it to generate an output.
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/// When disabled, the PWM slice will not produce any output.
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pub enable: bool,
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pub enable: bool,
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/// A fractional clock divider, represented as a fixed-point number with
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/// 8 integer bits and 4 fractional bits. It allows precise control over
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/// the PWM output frequency by gating the PWM counter increment.
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/// A higher value will result in a slower output frequency.
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pub divider: fixed::FixedU16<fixed::types::extra::U4>,
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pub divider: fixed::FixedU16<fixed::types::extra::U4>,
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/// The output on channel A goes high when `compare_a` is higher than the
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/// counter. A compare of 0 will produce an always low output, while a
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/// compare of `top` + 1 will produce an always high output.
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pub compare_a: u16,
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pub compare_a: u16,
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/// The output on channel B goes high when `compare_b` is higher than the
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/// counter. A compare of 0 will produce an always low output, while a
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/// compare of `top` + 1 will produce an always high output.
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pub compare_b: u16,
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pub compare_b: u16,
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/// The point at which the counter wraps, representing the maximum possible
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/// period. The counter will either wrap to 0 or reverse depending on the
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/// setting of `phase_correct`.
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pub top: u16,
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pub top: u16,
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}
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}
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@ -173,6 +197,9 @@ impl<'d, T: Channel> Pwm<'d, T> {
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});
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});
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}
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}
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/// Advances a slice’s output phase by one count while it is running
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/// by inserting or deleting pulses from the clock enable. The counter
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/// will not count faster than once per cycle.
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#[inline]
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#[inline]
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pub fn phase_advance(&mut self) {
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pub fn phase_advance(&mut self) {
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let p = self.inner.regs();
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let p = self.inner.regs();
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@ -180,6 +207,9 @@ impl<'d, T: Channel> Pwm<'d, T> {
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while p.csr().read().ph_adv() {}
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while p.csr().read().ph_adv() {}
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}
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}
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/// Retards a slice’s output phase by one count while it is running
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/// by deleting pulses from the clock enable. The counter will not
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/// count backward when clock enable is permenantly low
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#[inline]
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#[inline]
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pub fn phase_retard(&mut self) {
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pub fn phase_retard(&mut self) {
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let p = self.inner.regs();
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let p = self.inner.regs();
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