diff --git a/CHANGELOG.md b/CHANGELOG.md index bfba08301..cb7c17a6b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -184,6 +184,7 @@ Bottom level categories: #### DX12 - Don't depend on bind group and bind group layout entry order in HAL. This caused incorrect severely incorrect command execution and, in some cases, crashes. By @ErichDonGubler in [#5421](https://github.com/gfx-rs/wgpu/pull/5421). +- Shader Model 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, and 6.7 detection. By @atlv24 in [#5498](https://github.com/gfx-rs/wgpu/pull/5498) ## v0.19.3 (2024-03-01) diff --git a/naga-cli/src/bin/naga.rs b/naga-cli/src/bin/naga.rs index 36ca1e99a..eaa37b8fc 100644 --- a/naga-cli/src/bin/naga.rs +++ b/naga-cli/src/bin/naga.rs @@ -158,6 +158,13 @@ impl FromStr for ShaderModelArg { "50" => ShaderModel::V5_0, "51" => ShaderModel::V5_1, "60" => ShaderModel::V6_0, + "61" => ShaderModel::V6_1, + "62" => ShaderModel::V6_2, + "63" => ShaderModel::V6_3, + "64" => ShaderModel::V6_4, + "65" => ShaderModel::V6_5, + "66" => ShaderModel::V6_6, + "67" => ShaderModel::V6_7, _ => return Err(format!("Invalid value for --shader-model: {s}")), })) } diff --git a/naga/src/back/hlsl/mod.rs b/naga/src/back/hlsl/mod.rs index 392dc2c34..fe9740a2f 100644 --- a/naga/src/back/hlsl/mod.rs +++ b/naga/src/back/hlsl/mod.rs @@ -131,6 +131,13 @@ pub enum ShaderModel { V5_0, V5_1, V6_0, + V6_1, + V6_2, + V6_3, + V6_4, + V6_5, + V6_6, + V6_7, } impl ShaderModel { @@ -139,6 +146,13 @@ impl ShaderModel { Self::V5_0 => "5_0", Self::V5_1 => "5_1", Self::V6_0 => "6_0", + Self::V6_1 => "6_1", + Self::V6_2 => "6_2", + Self::V6_3 => "6_3", + Self::V6_4 => "6_4", + Self::V6_5 => "6_5", + Self::V6_6 => "6_6", + Self::V6_7 => "6_7", } } } diff --git a/wgpu-hal/src/dx12/adapter.rs b/wgpu-hal/src/dx12/adapter.rs index b417a88a6..2b7040720 100644 --- a/wgpu-hal/src/dx12/adapter.rs +++ b/wgpu-hal/src/dx12/adapter.rs @@ -181,6 +181,53 @@ impl super::Adapter { hr == 0 && features3.CastingFullyTypedFormatSupported != 0 }; + let shader_model = if dxc_container.is_none() { + naga::back::hlsl::ShaderModel::V5_1 + } else { + let mut versions = [ + crate::dx12::types::D3D_SHADER_MODEL_6_7, + crate::dx12::types::D3D_SHADER_MODEL_6_6, + crate::dx12::types::D3D_SHADER_MODEL_6_5, + crate::dx12::types::D3D_SHADER_MODEL_6_4, + crate::dx12::types::D3D_SHADER_MODEL_6_3, + crate::dx12::types::D3D_SHADER_MODEL_6_2, + crate::dx12::types::D3D_SHADER_MODEL_6_1, + crate::dx12::types::D3D_SHADER_MODEL_6_0, + crate::dx12::types::D3D_SHADER_MODEL_5_1, + ] + .iter(); + match loop { + if let Some(&sm) = versions.next() { + let mut sm = crate::dx12::types::D3D12_FEATURE_DATA_SHADER_MODEL { + HighestShaderModel: sm, + }; + if 0 == unsafe { + device.CheckFeatureSupport( + 7, // D3D12_FEATURE_SHADER_MODEL + &mut sm as *mut _ as *mut _, + mem::size_of::() + as _, + ) + } { + break sm.HighestShaderModel; + } + } else { + break crate::dx12::types::D3D_SHADER_MODEL_5_1; + } + } { + crate::dx12::types::D3D_SHADER_MODEL_5_1 => naga::back::hlsl::ShaderModel::V5_1, + crate::dx12::types::D3D_SHADER_MODEL_6_0 => naga::back::hlsl::ShaderModel::V6_0, + crate::dx12::types::D3D_SHADER_MODEL_6_1 => naga::back::hlsl::ShaderModel::V6_1, + crate::dx12::types::D3D_SHADER_MODEL_6_2 => naga::back::hlsl::ShaderModel::V6_2, + crate::dx12::types::D3D_SHADER_MODEL_6_3 => naga::back::hlsl::ShaderModel::V6_3, + crate::dx12::types::D3D_SHADER_MODEL_6_4 => naga::back::hlsl::ShaderModel::V6_4, + crate::dx12::types::D3D_SHADER_MODEL_6_5 => naga::back::hlsl::ShaderModel::V6_5, + crate::dx12::types::D3D_SHADER_MODEL_6_6 => naga::back::hlsl::ShaderModel::V6_6, + crate::dx12::types::D3D_SHADER_MODEL_6_7 => naga::back::hlsl::ShaderModel::V6_7, + _ => unreachable!(), + } + }; + let private_caps = super::PrivateCapabilities { instance_flags, heterogeneous_resource_heaps: options.ResourceHeapTier @@ -196,6 +243,7 @@ impl super::Adapter { casting_fully_typed_format_supported, // See https://github.com/gfx-rs/wgpu/issues/3552 suballocation_supported: !info.name.contains("Iris(R) Xe"), + shader_model, }; // Theoretically vram limited, but in practice 2^20 is the limit diff --git a/wgpu-hal/src/dx12/device.rs b/wgpu-hal/src/dx12/device.rs index 153dd6b90..f4539817d 100644 --- a/wgpu-hal/src/dx12/device.rs +++ b/wgpu-hal/src/dx12/device.rs @@ -1069,12 +1069,7 @@ impl crate::Device for super::Device { }, bind_group_infos, naga_options: hlsl::Options { - shader_model: match self.dxc_container { - // DXC - Some(_) => hlsl::ShaderModel::V6_0, - // FXC doesn't support SM 6.0 - None => hlsl::ShaderModel::V5_1, - }, + shader_model: self.private_caps.shader_model, binding_map, fake_missing_bindings: false, special_constants_binding, diff --git a/wgpu-hal/src/dx12/mod.rs b/wgpu-hal/src/dx12/mod.rs index 4f958943c..735732ef2 100644 --- a/wgpu-hal/src/dx12/mod.rs +++ b/wgpu-hal/src/dx12/mod.rs @@ -195,6 +195,7 @@ struct PrivateCapabilities { heap_create_not_zeroed: bool, casting_fully_typed_format_supported: bool, suballocation_supported: bool, + shader_model: naga::back::hlsl::ShaderModel, } #[derive(Default)] diff --git a/wgpu-hal/src/dx12/types.rs b/wgpu-hal/src/dx12/types.rs index b4ad38324..17b608b84 100644 --- a/wgpu-hal/src/dx12/types.rs +++ b/wgpu-hal/src/dx12/types.rs @@ -41,3 +41,25 @@ winapi::STRUCT! { BarycentricsSupported: winapi::shared::minwindef::BOOL, } } + +winapi::ENUM! { + enum D3D_SHADER_MODEL { + D3D_SHADER_MODEL_NONE = 0, + D3D_SHADER_MODEL_5_1 = 0x51, + D3D_SHADER_MODEL_6_0 = 0x60, + D3D_SHADER_MODEL_6_1 = 0x61, + D3D_SHADER_MODEL_6_2 = 0x62, + D3D_SHADER_MODEL_6_3 = 0x63, + D3D_SHADER_MODEL_6_4 = 0x64, + D3D_SHADER_MODEL_6_5 = 0x65, + D3D_SHADER_MODEL_6_6 = 0x66, + D3D_SHADER_MODEL_6_7 = 0x67, + D3D_HIGHEST_SHADER_MODEL = 0x67, + } +} + +winapi::STRUCT! { + struct D3D12_FEATURE_DATA_SHADER_MODEL { + HighestShaderModel: D3D_SHADER_MODEL, + } +}