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Fix read-write buffer barrier

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This commit is contained in:
Dzmitry Malyshau 2021-09-02 16:04:40 -04:00 committed by Dzmitry Malyshau
parent d23288e455
commit 663f64c571
3 changed files with 6 additions and 5 deletions
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2
wgpu-core/src/device/mod.rs
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@ -1252,7 +1252,7 @@ impl<A: HalApi> Device<A> {
if read_only { if read_only {
hal::BufferUses::STORAGE_READ hal::BufferUses::STORAGE_READ
} else { } else {
hal::BufferUses::STORAGE_WRITE hal::BufferUses::STORAGE_READ | hal::BufferUses::STORAGE_WRITE
}, },
limits.max_storage_buffer_binding_size, limits.max_storage_buffer_binding_size,
), ),

7
wgpu-hal/src/dx12/conv.rs
View File

@ -323,12 +323,11 @@ pub fn map_buffer_usage_to_state(usage: crate::BufferUses) -> d3d12::D3D12_RESOU
if usage.intersects(Bu::VERTEX | Bu::UNIFORM) { if usage.intersects(Bu::VERTEX | Bu::UNIFORM) {
state |= d3d12::D3D12_RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER; state |= d3d12::D3D12_RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER;
} }
if usage.intersects(Bu::STORAGE_READ) {
state |= d3d12::D3D12_RESOURCE_STATE_PIXEL_SHADER_RESOURCE
| d3d12::D3D12_RESOURCE_STATE_NON_PIXEL_SHADER_RESOURCE;
}
if usage.intersects(Bu::STORAGE_WRITE) { if usage.intersects(Bu::STORAGE_WRITE) {
state |= d3d12::D3D12_RESOURCE_STATE_UNORDERED_ACCESS; state |= d3d12::D3D12_RESOURCE_STATE_UNORDERED_ACCESS;
} else if usage.intersects(Bu::STORAGE_READ) {
state |= d3d12::D3D12_RESOURCE_STATE_PIXEL_SHADER_RESOURCE
| d3d12::D3D12_RESOURCE_STATE_NON_PIXEL_SHADER_RESOURCE;
} }
if usage.intersects(Bu::INDIRECT) { if usage.intersects(Bu::INDIRECT) {
state |= d3d12::D3D12_RESOURCE_STATE_INDIRECT_ARGUMENT; state |= d3d12::D3D12_RESOURCE_STATE_INDIRECT_ARGUMENT;

2
wgpu-hal/src/lib.rs
View File

@ -609,6 +609,7 @@ bitflags::bitflags! {
Self::INDEX.bits | Self::VERTEX.bits | Self::UNIFORM.bits | Self::INDEX.bits | Self::VERTEX.bits | Self::UNIFORM.bits |
Self::STORAGE_READ.bits | Self::INDIRECT.bits; Self::STORAGE_READ.bits | Self::INDIRECT.bits;
/// The combination of exclusive usages (write-only and read-write). /// The combination of exclusive usages (write-only and read-write).
/// These usages may still show up with others, but can't automatically be combined.
const EXCLUSIVE = Self::MAP_WRITE.bits | Self::COPY_DST.bits | Self::STORAGE_WRITE.bits; const EXCLUSIVE = Self::MAP_WRITE.bits | Self::COPY_DST.bits | Self::STORAGE_WRITE.bits;
/// The combination of all usages that the are guaranteed to be be ordered by the hardware. /// The combination of all usages that the are guaranteed to be be ordered by the hardware.
/// If a usage is not ordered, then even if it doesn't change between draw calls, there /// If a usage is not ordered, then even if it doesn't change between draw calls, there
@ -631,6 +632,7 @@ bitflags::bitflags! {
/// The combination of usages that can be used together (read-only). /// The combination of usages that can be used together (read-only).
const INCLUSIVE = Self::COPY_SRC.bits | Self::RESOURCE.bits | Self::DEPTH_STENCIL_READ.bits; const INCLUSIVE = Self::COPY_SRC.bits | Self::RESOURCE.bits | Self::DEPTH_STENCIL_READ.bits;
/// The combination of exclusive usages (write-only and read-write). /// The combination of exclusive usages (write-only and read-write).
/// These usages may still show up with others, but can't automatically be combined.
const EXCLUSIVE = Self::COPY_DST.bits | Self::COLOR_TARGET.bits | Self::DEPTH_STENCIL_WRITE.bits | Self::STORAGE_READ.bits | Self::STORAGE_WRITE.bits; const EXCLUSIVE = Self::COPY_DST.bits | Self::COLOR_TARGET.bits | Self::DEPTH_STENCIL_WRITE.bits | Self::STORAGE_READ.bits | Self::STORAGE_WRITE.bits;
/// The combination of all usages that the are guaranteed to be be ordered by the hardware. /// The combination of all usages that the are guaranteed to be be ordered by the hardware.
/// If a usage is not ordered, then even if it doesn't change between draw calls, there /// If a usage is not ordered, then even if it doesn't change between draw calls, there