rust/compiler/rustc_codegen_cranelift/src
bors 7a17f577b3 Auto merge of #112157 - erikdesjardins:align, r=nikic
Resurrect: rustc_target: Add alignment to indirectly-passed by-value types, correcting the alignment of byval on x86 in the process.

Same as #111551, which I [accidentally closed](https://github.com/rust-lang/rust/pull/111551#issuecomment-1571222612) :/

---

This resurrects PR #103830, which has sat idle for a while.

Beyond #103830, this also:
- fixes byval alignment for types containing vectors on Darwin (see `tests/codegen/align-byval-vector.rs`)
- fixes byval alignment for overaligned types on x86 Windows (see `tests/codegen/align-byval.rs`)
- fixes ABI for types with 128bit requested alignment on ARM64 Linux (see `tests/codegen/aarch64-struct-align-128.rs`)

r? `@nikic`

---

`@pcwalton's` original PR description is reproduced below:

Commit 88e4d2c from five years ago removed
support for alignment on indirectly-passed arguments because of problems with
the `i686-pc-windows-msvc` target. Unfortunately, the `memcpy` optimizations I
recently added to LLVM 16 depend on this to forward `memcpy`s. This commit
attempts to fix the problems with `byval` parameters on that target and now
correctly adds the `align` attribute.

The problem is summarized in [this comment] by `@eddyb.` Briefly, 32-bit x86 has
special alignment rules for `byval` parameters: for the most part, their
alignment is forced to 4. This is not well-documented anywhere but in the Clang
source. I looked at the logic in Clang `TargetInfo.cpp` and tried to replicate
it here. The relevant methods in that file are
`X86_32ABIInfo::getIndirectResult()` and
`X86_32ABIInfo::getTypeStackAlignInBytes()`. The `align` parameter attribute
for `byval` parameters in LLVM must match the platform ABI, or miscompilations
will occur. Note that this doesn't use the approach suggested by eddyb, because
I felt it was overkill to store the alignment in `on_stack` when special
handling is really only needed for 32-bit x86.

As a side effect, this should fix #80127, because it will make the `align`
parameter attribute for `byval` parameters match the platform ABI on LLVM
x86-64.

[this comment]: #80822 (comment)
2023-07-15 15:39:53 +00:00
..
abi Auto merge of #112157 - erikdesjardins:align, r=nikic 2023-07-15 15:39:53 +00:00
debuginfo Avoid unnecessary line lookup. 2023-06-29 11:26:39 +10:00
driver Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into sync_cg_clif-2023-06-15 2023-06-15 17:56:01 +00:00
intrinsics refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
optimize Merge commit '598f0909568a51de8a2d1148f55a644fd8dffad0' into sync_cg_clif-2023-01-24 2023-01-24 18:56:42 +01:00
allocator.rs Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into sync_cg_clif-2023-06-15 2023-06-15 17:56:01 +00:00
analyze.rs Split {Idx, IndexVec, IndexSlice} into their own modules 2023-04-24 13:53:35 +00:00
archive.rs Rewrite LLVM's archive writer in Rust 2022-11-26 19:35:32 +00:00
base.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
cast.rs Merge commit 'ef07e8e60f994ec014d049a95591426fb92ebb79' into sync_cg_clif-2023-04-29 2023-04-29 12:00:43 +00:00
codegen_i128.rs Move TyCtxt::mk_x to Ty::new_x where applicable 2023-07-05 20:27:07 +01:00
common.rs Move TyCtxt::mk_x to Ty::new_x where applicable 2023-07-05 20:27:07 +01:00
compiler_builtins.rs Merge commit 'dec0daa8f6d0a0e1c702f169abb6bf3eee198c67' into sync_cg_clif-2023-03-15 2023-03-15 14:41:48 +00:00
concurrency_limiter.rs Restrict From<S> for {D,Subd}iagnosticMessage. 2023-05-03 08:44:39 +10:00
config.rs Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into sync_cg_clif-2023-06-15 2023-06-15 17:56:01 +00:00
constant.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
discriminant.rs Remove from cranelift too. 2023-04-14 16:26:11 +00:00
global_asm.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
inline_asm.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
lib.rs Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into sync_cg_clif-2023-06-15 2023-06-15 17:56:01 +00:00
linkage.rs Sync rustc_codegen_cranelift 'ddd4ce25535cf71203ba3700896131ce55fde795' 2021-04-30 14:49:58 +02:00
main_shim.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
num.rs Move TyCtxt::mk_x to Ty::new_x where applicable 2023-07-05 20:27:07 +01:00
pointer.rs Merge commit 'dec0daa8f6d0a0e1c702f169abb6bf3eee198c67' into sync_cg_clif-2023-03-15 2023-03-15 14:41:48 +00:00
pretty_clif.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
toolchain.rs Merge commit 'e9d1a0a7b0b28dd422f1a790ccde532acafbf193' into sync_cg_clif-2022-08-24 2022-08-24 18:40:58 +02:00
trap.rs Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into sync_cg_clif-2023-06-15 2023-06-15 17:56:01 +00:00
unsize.rs Rename adjustment::PointerCast and variants using it to PointerCoercion 2023-07-07 18:17:16 +02:00
value_and_place.rs refactor(rustc_middle): Substs -> GenericArg 2023-07-14 13:27:35 +01:00
vtable.rs Move mir::Fieldabi::FieldIdx 2023-03-28 22:22:37 -07:00