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1aa01927d3
Support input/output in vector registers of PowerPC inline assembly This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types as input/output. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` | | PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` | In addition to floats and `core::simd` types listed above, `core::arch` types and custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types and relevant target features are currently unstable. r? `@Amanieu` `@rustbot` label +O-PowerPC +A-inline-assembly |
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| .. | ||
| aarch64-clobbers.rs | ||
| avr-clobbers.rs | ||
| foo.s | ||
| global_asm_include.rs | ||
| global_asm_x2.rs | ||
| global_asm.rs | ||
| goto.rs | ||
| hexagon-clobbers.rs | ||
| may_unwind.rs | ||
| maybe-uninit.rs | ||
| msp430-clobbers.rs | ||
| multiple-options.rs | ||
| options.rs | ||
| powerpc-clobbers.rs | ||
| riscv-clobbers.rs | ||
| s390x-clobbers.rs | ||
| sanitize-llvm.rs | ||
| sparc-clobbers.rs | ||
| x86-clobber_abi.rs | ||
| x86-clobbers.rs | ||
| x86-target-clobbers.rs | ||