mirror of
https://github.com/rust-lang/rust.git
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6cd17ff4d2
This adds comparisons among the compiler-builtins function, system functions if available, and optionally handwritten assembly. These also help us identify inconsistencies between this crate and system functions, which may otherwise go unnoticed if intrinsics get lowered to inline operations rather than library calls.
548 lines
12 KiB
Rust
548 lines
12 KiB
Rust
#![feature(f128)]
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#![allow(improper_ctypes)]
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use compiler_builtins::float::conv;
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use criterion::{criterion_group, criterion_main, Criterion};
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use testcrate::float_bench;
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/* unsigned int -> float */
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float_bench! {
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name: conv_u32_f32,
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sig: (a: u32) -> f32,
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crate_fn: conv::__floatunsisf,
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sys_fn: __floatunsisf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f32;
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asm!(
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"mov {tmp:e}, {a:e}",
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"cvtsi2ss {ret}, {tmp}",
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a = in(reg) a,
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tmp = out(reg) _,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f32;
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asm!(
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"ucvtf {ret:s}, {a:w}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_u32_f64,
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sig: (a: u32) -> f64,
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crate_fn: conv::__floatunsidf,
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sys_fn: __floatunsidf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f64;
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asm!(
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"mov {tmp:e}, {a:e}",
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"cvtsi2sd {ret}, {tmp}",
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a = in(reg) a,
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tmp = out(reg) _,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f64;
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asm!(
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"ucvtf {ret:d}, {a:w}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_u64_f32,
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sig: (a: u64) -> f32,
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crate_fn: conv::__floatundisf,
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sys_fn: __floatundisf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: f32;
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asm!(
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"ucvtf {ret:s}, {a:x}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_u64_f64,
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sig: (a: u64) -> f64,
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crate_fn: conv::__floatundidf,
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sys_fn: __floatundidf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: f64;
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asm!(
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"ucvtf {ret:d}, {a:x}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_u128_f32,
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sig: (a: u128) -> f32,
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crate_fn: conv::__floatuntisf,
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sys_fn: __floatuntisf,
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sys_available: all(),
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asm: []
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}
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float_bench! {
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name: conv_u128_f64,
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sig: (a: u128) -> f64,
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crate_fn: conv::__floatuntidf,
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sys_fn: __floatuntidf,
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sys_available: all(),
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asm: []
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}
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/* signed int -> float */
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float_bench! {
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name: conv_i32_f32,
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sig: (a: i32) -> f32,
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crate_fn: conv::__floatsisf,
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sys_fn: __floatsisf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f32;
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asm!(
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"cvtsi2ss {ret}, {a:e}",
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a = in(reg) a,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f32;
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asm!(
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"scvtf {ret:s}, {a:w}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_i32_f64,
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sig: (a: i32) -> f64,
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crate_fn: conv::__floatsidf,
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sys_fn: __floatsidf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f64;
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asm!(
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"cvtsi2sd {ret}, {a:e}",
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a = in(reg) a,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f64;
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asm!(
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"scvtf {ret:d}, {a:w}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_i64_f32,
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sig: (a: i64) -> f32,
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crate_fn: conv::__floatdisf,
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sys_fn: __floatdisf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f32;
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asm!(
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"cvtsi2ss {ret}, {a:r}",
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a = in(reg) a,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f32;
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asm!(
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"scvtf {ret:s}, {a:x}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_i64_f64,
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sig: (a: i64) -> f64,
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crate_fn: conv::__floatdidf,
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sys_fn: __floatdidf,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "x86_64")] {
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let ret: f64;
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asm!(
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"cvtsi2sd {ret}, {a:r}",
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a = in(reg) a,
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ret = lateout(xmm_reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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#[cfg(target_arch = "aarch64")] {
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let ret: f64;
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asm!(
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"scvtf {ret:d}, {a:x}",
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a = in(reg) a,
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ret = lateout(vreg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_i128_f32,
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sig: (a: i128) -> f32,
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crate_fn: conv::__floattisf,
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sys_fn: __floattisf,
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sys_available: all(),
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asm: []
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}
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float_bench! {
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name: conv_i128_f64,
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sig: (a: i128) -> f64,
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crate_fn: conv::__floattidf,
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sys_fn: __floattidf,
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sys_available: all(),
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asm: []
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}
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/* float -> unsigned int */
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_u32,
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sig: (a: f32) -> u32,
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crate_fn: conv::__fixunssfsi,
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sys_fn: __fixunssfsi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: u32;
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asm!(
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"fcvtzu {ret:w}, {a:s}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_u64,
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sig: (a: f32) -> u64,
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crate_fn: conv::__fixunssfdi,
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sys_fn: __fixunssfdi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: u64;
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asm!(
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"fcvtzu {ret:x}, {a:s}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_u128,
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sig: (a: f32) -> u128,
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crate_fn: conv::__fixunssfti,
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sys_fn: __fixunssfti,
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sys_available: all(),
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asm: []
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}
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float_bench! {
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name: conv_f64_u32,
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sig: (a: f64) -> u32,
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crate_fn: conv::__fixunsdfsi,
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sys_fn: __fixunsdfsi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: u32;
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asm!(
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"fcvtzu {ret:w}, {a:d}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_f64_u64,
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sig: (a: f64) -> u64,
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crate_fn: conv::__fixunsdfdi,
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sys_fn: __fixunsdfdi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: u64;
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asm!(
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"fcvtzu {ret:x}, {a:d}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_f64_u128,
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sig: (a: f64) -> u128,
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crate_fn: conv::__fixunsdfti,
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sys_fn: __fixunsdfti,
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sys_available: all(),
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asm: []
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}
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/* float -> signed int */
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_i32,
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sig: (a: f32) -> i32,
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crate_fn: conv::__fixsfsi,
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sys_fn: __fixsfsi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: i32;
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asm!(
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"fcvtzs {ret:w}, {a:s}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_i64,
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sig: (a: f32) -> i64,
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crate_fn: conv::__fixsfdi,
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sys_fn: __fixsfdi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: i64;
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asm!(
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"fcvtzs {ret:x}, {a:s}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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float_bench! {
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name: conv_f32_i128,
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sig: (a: f32) -> i128,
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crate_fn: conv::__fixsfti,
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sys_fn: __fixsfti,
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sys_available: all(),
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asm: []
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}
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float_bench! {
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name: conv_f64_i32,
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sig: (a: f64) -> i32,
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crate_fn: conv::__fixdfsi,
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sys_fn: __fixdfsi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: i32;
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asm!(
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"fcvtzs {ret:w}, {a:d}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_f64_i64,
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sig: (a: f64) -> i64,
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crate_fn: conv::__fixdfdi,
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sys_fn: __fixdfdi,
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sys_available: all(),
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asm: [
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#[cfg(target_arch = "aarch64")] {
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let ret: i64;
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asm!(
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"fcvtzs {ret:x}, {a:d}",
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a = in(vreg) a,
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ret = lateout(reg) ret,
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options(nomem, nostack, pure),
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);
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ret
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};
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],
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}
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float_bench! {
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name: conv_f64_i128,
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sig: (a: f64) -> i128,
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crate_fn: conv::__fixdfti,
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sys_fn: __fixdfti,
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sys_available: all(),
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asm: []
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}
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criterion_group!(
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float_conv,
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conv_u32_f32,
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conv_u32_f64,
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conv_u64_f32,
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conv_u64_f64,
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conv_u128_f32,
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conv_u128_f64,
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conv_i32_f32,
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conv_i32_f64,
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conv_i64_f32,
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conv_i64_f64,
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conv_i128_f32,
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conv_i128_f64,
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conv_f64_u32,
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conv_f64_u64,
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conv_f64_u128,
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conv_f64_i32,
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conv_f64_i64,
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conv_f64_i128,
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);
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// FIXME: ppc64le has a sporadic overflow panic in the crate functions
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// <https://github.com/rust-lang/compiler-builtins/issues/617#issuecomment-2125914639>
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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criterion_group!(
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float_conv_not_ppc64le,
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conv_f32_u32,
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conv_f32_u64,
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conv_f32_u128,
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conv_f32_i32,
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conv_f32_i64,
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conv_f32_i128,
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);
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#[cfg(all(target_arch = "powerpc64", target_endian = "little"))]
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criterion_main!(float_conv);
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#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))]
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criterion_main!(float_conv, float_conv_not_ppc64le);
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