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5926e82dd1
rust/compiler/rustc_middle
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bors 5926e82dd1 Auto merge of #124780 - Mark-Simulacrum:lockless-cache, r=lcnr 
Improve VecCache under parallel frontend

This replaces the single Vec allocation with a series of progressively larger buckets. With the cfg for parallel enabled but with -Zthreads=1, this looks like a slight regression in i-count and cycle counts (~1%).

With the parallel frontend at -Zthreads=4, this is an improvement (-5% wall-time from 5.788 to 5.4688 on libcore) than our current Lock-based approach, likely due to reducing the bouncing of the cache line holding the lock. At -Zthreads=32 it's a huge improvement (-46%: 8.829 -> 4.7319 seconds).

try-job: i686-gnu-nopt
try-job: dist-x86_64-linux
2024-11-19 02:07:48 +00:00
..
src Auto merge of #124780 - Mark-Simulacrum:lockless-cache, r=lcnr 2024-11-19 02:07:48 +00:00
Cargo.toml Delete the cfg(not(parallel)) serial compiler 2024-11-12 13:38:58 +00:00
messages.ftl Tweak E0320 overflow error wording 2024-11-05 21:54:45 +00:00
README.md

README.md

For more information about how rustc works, see the rustc dev guide.