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Support input/output in vector registers of s390x inline assembly (under asm_experimental_reg feature) This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output. This is unstable and gated under new `#![feature(asm_experimental_reg)]` (tracking issue: https://github.com/rust-lang/rust/issues/133416). If the feature is not enabled, only clober is supported as before. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` | This matches the list of types that are supported by the vector registers in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313 In addition to `core::simd` types and floats listed above, custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable. Currently there is no SIMD type for s390x in `core::arch`, but this is tracked in https://github.com/rust-lang/rust/issues/130869. cc https://github.com/rust-lang/rust/issues/130869 about vector facility support in s390x cc https://github.com/rust-lang/rust/issues/125398 & https://github.com/rust-lang/rust/issues/116909 about f128 support in asm `@rustbot` label +O-SystemZ +A-inline-assembly |
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| .. | ||
| back | ||
| coverageinfo | ||
| debuginfo | ||
| llvm | ||
| abi.rs | ||
| allocator.rs | ||
| asm.rs | ||
| attributes.rs | ||
| base.rs | ||
| builder.rs | ||
| callee.rs | ||
| common.rs | ||
| consts.rs | ||
| context.rs | ||
| declare.rs | ||
| errors.rs | ||
| intrinsic.rs | ||
| lib.rs | ||
| llvm_util.rs | ||
| mono_item.rs | ||
| type_.rs | ||
| type_of.rs | ||
| va_arg.rs | ||
| value.rs | ||