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rust/compiler/rustc_codegen_llvm
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Nikita Popov 369fff6c06 Implicitly enable evex512 if avx512 is enabled 
LLVM 18 requires the evex512 feature to allow use of zmm registers.
LLVM automatically sets it when using a generic CPU, but not when
`-C target-cpu` is specified. This will result either in backend
legalization crashes, or code unexpectedly using ymm instead of
zmm registers.

For now, make sure that `avx512*` features imply `evex512`. Long
term we'll probably have to deal with the AVX10 mess somehow.
2024-02-14 16:26:20 +01:00
..
src Implicitly enable evex512 if avx512 is enabled 2024-02-14 16:26:20 +01:00
Cargo.toml Update measureme crate to version 11 2024-01-13 16:32:03 +01:00
messages.ftl Emit a diagnostic for invalid target options 2024-02-03 22:03:25 -05:00
README.md mv compiler to compiler/ 2020-08-30 18:45:07 +03:00

README.md

The codegen crate contains the code to convert from MIR into LLVM IR, and then from LLVM IR into machine code. In general it contains code that runs towards the end of the compilation process.

For more information about how codegen works, see the rustc dev guide.