Commit Graph

483 Commits

Author SHA1 Message Date
Matthias Krüger
7c2d57e0fa couple of clippy::complexity fixes 2022-04-13 22:51:34 +02:00
Pietro Albini
181d28bb61
trivial cfg(bootstrap) changes 2022-04-05 23:18:40 +02:00
Oli Scherer
d32ce37a17 Mark scalar layout unions so that backends that do not support partially initialized scalars can special case them. 2022-04-05 13:18:21 +00:00
Loïc BRANSTETT
1a1f5b89a4 Cleanup after some refactoring in rustc_target 2022-04-03 21:29:57 +02:00
Loïc BRANSTETT
c16a558f24 Replace LinkArgs with Cow<'static, str> 2022-04-03 21:29:57 +02:00
Loïc BRANSTETT
ce61d4044d Replace every Vec in Target(Options) with it's Cow equivalent 2022-04-03 21:29:57 +02:00
Loïc BRANSTETT
ccff48f97b Replace every String in Target(Options) with Cow<'static, str> 2022-04-03 21:29:57 +02:00
Dylan DPC
46a4754df0
Rollup merge of #95430 - ChrisDenton:disable-tls-i686-msvc, r=nagisa
Disable #[thread_local] support on i686-pc-windows-msvc

Fixes #95429
2022-04-02 03:34:22 +02:00
bors
df20355fa9 Auto merge of #95456 - RalfJung:size, r=oli-obk
allow large Size again

This basically reverts most of https://github.com/rust-lang/rust/pull/80042, and instead does the panic in `bits()` with a `#[cold]` function to make sure it does not get inlined.

https://github.com/rust-lang/rust/pull/80042 added a comment about an invariant ("The top 3 bits are ALWAYS zero") that is not actually enforced, and if it were enforced that would be a problem for https://github.com/rust-lang/rust/pull/95388. So I think we should not have that invariant, and I adjusted the code accordingly.

r? `@oli-obk` Cc `@sivadeilra`
2022-03-31 10:33:56 +00:00
Yuri Astrakhan
8d7b124c1f a few mode feedback fixes per @bjorn3 2022-03-30 17:28:19 -04:00
Yuri Astrakhan
5160f8f843 Spellchecking compiler comments
This PR cleans up the rest of the spelling mistakes in the compiler comments. This PR does not change any literal or code spelling issues.
2022-03-30 15:14:15 -04:00
Ralf Jung
2799885ed0 allow large Size again 2022-03-29 22:25:38 -04:00
Chris Denton
017a092f45
Disable #[thread_local] support on i686-pc-windows-msvc 2022-03-29 12:37:20 +01:00
Dylan DPC
2ab4ad5f26
Rollup merge of #95341 - Meziu:armv6k-3ds-target, r=nagisa
ARMv6K Horizon OS has_thread_local support

cc. ```@ian-h-chamberlain```
cc. ```@AzureMarker```

Being an ARM target, it has always had built-in support for `#[thread_local]`. This PR comes in just now because we were testing `std::thread` support with `thread_local_dtor`s. This will hopefully be the last PR for the target specification, unless anymore features will be needed as time goes on.
2022-03-27 05:36:11 +02:00
Meziu
419b6309a9
Merge pull request #16 from ian-h-chamberlain/feature/target-thread-local
Enable #[thread_local] on armv6k-nintendo-3ds
2022-03-26 20:49:19 +01:00
Ian Chamberlain
78294371c4
Enable #[thread_local] on armv6k-nintendo-3ds 2022-03-26 09:29:01 -04:00
Martin Kröning
335d196498 Remove hermitkernel targets
RustyHermit now maintains custom json targets, which are distributed with the kernel. [1]

[1]: https://github.com/hermitcore/libhermit-rs/pull/395
2022-03-25 11:52:11 +01:00
Dylan DPC
67d6cc6ef3
Rollup merge of #91608 - workingjubilee:fold-neon-fp, r=nagisa,Amanieu
Fold aarch64 feature +fp into +neon

Arm's FEAT_FP and Feat_AdvSIMD describe the same thing on AArch64:
The Neon unit, which handles both floating point and SIMD instructions.
Moreover, a configuration for AArch64 must include both or neither.
Arm says "entirely proprietary" toolchains may omit floating point:
https://developer.arm.com/documentation/102374/0101/Data-processing---floating-point
In the Programmer's Guide for Armv8-A, Arm says AArch64 can have
both FP and Neon or neither in custom implementations:
https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON

In "Bare metal boot code for Armv8-A", enabling Neon and FP
is just disabling the same trap flag:
https://developer.arm.com/documentation/dai0527/a

In an unlikely future where "Neon and FP" become unrelated,
we can add "[+-]fp" as its own feature flag.
Until then, we can simplify programming with Rust on AArch64 by
folding both into "[+-]neon", which is valid as it supersets both.

"[+-]neon" is retained for niche uses such as firmware, kernels,
"I just hate floats", and so on.

I am... pretty sure no one is relying on this.

An argument could be made that, as we are not an "entirely proprietary" toolchain, we should not support AArch64 without floats at all. I think that's a bit excessive. However, I want to recognize the intent: programming for AArch64 should be simplified where possible. For x86-64, programmers regularly set up illegal feature configurations because it's hard to understand them, see https://github.com/rust-lang/rust/issues/89586. And per the above notes, plus the discussion in https://github.com/rust-lang/rust/issues/86941, there should be no real use cases for leaving these features split: the two should in fact always go together.

- Fixes rust-lang/rust#95002.
- Fixes rust-lang/rust#95064.
- Fixes rust-lang/rust#95122.
2022-03-23 03:05:28 +01:00
Jubilee Young
b807d5970b Fold aarch64 feature +fp into +neon
Arm's FEAT_FP and Feat_AdvSIMD describe the same thing on AArch64:
The Neon unit, which handles both floating point and SIMD instructions.
Moreover, a configuration for AArch64 must include both or neither.
Arm says "entirely proprietary" toolchains may omit floating point:
https://developer.arm.com/documentation/102374/0101/Data-processing---floating-point
In the Programmer's Guide for Armv8-A, Arm says AArch64 can have
both FP and Neon or neither in custom implementations:
https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON

In "Bare metal boot code for Armv8-A", enabling Neon and FP
is just disabling the same trap flag:
https://developer.arm.com/documentation/dai0527/a

In an unlikely future where "Neon and FP" become unrelated,
we can add "[+-]fp" as its own feature flag.
Until then, we can simplify programming with Rust on AArch64 by
folding both into "[+-]neon", which is valid as it supersets both.

"[+-]neon" is retained for niche uses such as firmware, kernels,
"I just hate floats", and so on.
2022-03-22 15:14:33 -07:00
codehorseman
01dbfb3eb2 resolve the conflict in compiler/rustc_session/src/parse.rs
Signed-off-by: codehorseman <cricis@yeah.net>
2022-03-16 20:12:30 +08:00
ridwanabdillahi
eae68350c8 Add support for targeting riscv32im-unknown-none-elf
Update riscv32im-unknown-none-elf to Tier2 support.

Downgrade to Tier 3 platform support.
2022-03-09 13:51:29 -08:00
Nicholas Nethercote
4f008e06c3 Clarify Layout interning.
`Layout` is another type that is sometimes interned, sometimes not, and
we always use references to refer to it so we can't take any advantage
of the uniqueness properties for hashing or equality checks.

This commit renames `Layout` as `LayoutS`, and then introduces a new
`Layout` that is a newtype around an `Interned<LayoutS>`. It also
interns more layouts than before. Previously layouts within layouts
(via the `variants` field) were never interned, but now they are. Hence
the lifetime on the new `Layout` type.

Unlike other interned types, these ones are in `rustc_target` instead of
`rustc_middle`. This reflects the existing structure of the code, which
does layout-specific stuff in `rustc_target` while `TyAndLayout` is
generic over the `Ty`, allowing the type-specific stuff to occur in
`rustc_middle`.

The commit also adds a `HashStable` impl for `Interned`, which was
needed. It hashes the contents, unlike the `Hash` impl which hashes the
pointer.
2022-03-07 13:41:47 +11:00
bors
0cbef1c6a7 Auto merge of #94601 - csmoe:android-asan, r=nagisa
add address sanitizer fo android

We have been being using asan to debug the rust/cpp/c mixed android application in production for months: recompile the rust library with a patched rustc, everything just works fine. The patch is really small thanks to `@nagisa` 's refactoring in https://github.com/rust-lang/rust/pull/81866

r? `@nagisa`
2022-03-05 22:52:08 +00:00
Dylan DPC
afa85f0841
Rollup merge of #94362 - Urgau:check-cfg-values, r=petrochenkov
Add well known values to `--check-cfg` implementation

This pull-request adds well known values for the well known names via `--check-cfg=values()`.

[RFC 3013: Checking conditional compilation at compile time](https://rust-lang.github.io/rfcs/3013-conditional-compilation-checking.html#checking-conditional-compilation-at-compile-time) doesn't define this at all, but this seems a nice improvement.
The activation is done by a empty `values()` (new syntax) similar to `names()` except that `names(foo)` also activate well known names while `values(aa, "aa", "kk")` would not.

As stated this use a different activation logic because well known values for the well known names are not always sufficient.
In fact this is problematic for every `target_*` cfg because of non builtin targets, as the current implementation use those built-ins targets to create the list the well known values.

The implementation is straight forward, first we gather (if necessary) all the values (lazily or not) and then we apply them.

r? ```@petrochenkov```
2022-03-04 22:58:34 +01:00
csmoe
6d41565726 add address sanitizer fo android 2022-03-04 10:21:43 +00:00
Loïc BRANSTETT
4aa92aff05 Add well known values to --check-cfg implementation 2022-03-04 11:15:38 +01:00
Dylan DPC
79c71d1f9e
Rollup merge of #94339 - Amanieu:arm-d32, r=nagisa
ARM: Only allow using d16-d31 with asm! when supported by the target

Support can be determined by checking for the "d32" LLVM feature.

r? ```````````````@nagisa```````````````
2022-03-04 02:06:40 +01:00
bors
edda7e959d Auto merge of #94216 - psumbera:sparc64-abi-fix2, r=nagisa
more complete sparc64 ABI fix for aggregates with floating point members

Previous fix didn't handle nested structures at all.
2022-02-28 11:54:17 +00:00
Amanieu d'Antras
7cee1b4aeb ARM: Only allow using d16-d31 with asm! when supported by the target
Support can be determined by checking for the "d32" LLVM feature.
2022-02-24 22:37:53 +00:00
Scott Mabin
65614e91ad riscv32imc_esp_espidf: set max_atomic_width to 64 2022-02-23 13:11:26 +00:00
Amanieu d'Antras
fb5539b475 Add tests 2022-02-21 18:28:22 +00:00
Amanieu d'Antras
fc41d4bf35 Take CodegenFnAttrs into account when validating asm! register operands
Checking of asm! register operands now properly takes function
attributes such as #[target_feature] and #[instruction_set] into
account.
2022-02-21 18:28:22 +00:00
Amanieu d'Antras
1ceb104851 On ARM, use relocation_model to detect whether r9 should be reserved
The previous approach of checking for the reserve-r9 target feature
didn't actually work because LLVM only sets this feature very late when
initializing the per-function subtarget.
2022-02-21 18:28:22 +00:00
Amanieu d'Antras
2e8a7663b4 Simplify gating of BPF w registers behind the alu32 target feature
This is already handled by supported_types().
2022-02-21 18:28:22 +00:00
Petr Sumbera
0d200116d3 formatting fixes 2022-02-21 14:23:22 +01:00
Petr Sumbera
a29477c9ca more complete sparc64 ABI fix for aggregates with floating point members
Previous fix didn't handle nested structures at all.
2022-02-21 13:49:36 +01:00
Matthias Krüger
f2d6770f77
Rollup merge of #94146 - est31:let_else, r=cjgillot
Adopt let else in more places

Continuation of #89933, #91018, #91481, #93046, #93590, #94011.

I have extended my clippy lint to also recognize tuple passing and match statements. The diff caused by fixing it is way above 1 thousand lines. Thus, I split it up into multiple pull requests to make reviewing easier. This is the biggest of these PRs and handles the changes outside of rustdoc, rustc_typeck, rustc_const_eval, rustc_trait_selection, which were handled in PRs #94139, #94142, #94143, #94144.
2022-02-20 00:37:34 +01:00
est31
2ef8af6619 Adopt let else in more places 2022-02-19 17:27:43 +01:00
Matthias Krüger
cb35370557
Rollup merge of #93877 - Amanieu:asm_fixes, r=nagisa
asm: Allow the use of r8-r14 as clobbers on Thumb1

Previously these were entirely disallowed, except for r11 which was allowed by accident.

cc `@hudson-ayers`
2022-02-18 23:23:08 +01:00
Matthias Krüger
32c8acd769
Rollup merge of #93814 - Itus-Shield:mips64-openwrt, r=bjorn3
mips64-openwrt-linux-musl: correct soft-foat

MIPS64 targets under OpenWrt require soft-float fpu support.

Rust-lang requires soft-float defined in tuple definition and
isn't over-ridden by toolchain compile-time CFLAGS/LDFLAGS

Set explicit soft-float for tuple.

Signed-off-by: Donald Hoskins <grommish@gmail.com>
2022-02-18 23:23:06 +01:00
Matthias Krüger
0bb72a2c66
Rollup merge of #91675 - ivanloz:memtagsan, r=nagisa
Add MemTagSanitizer Support

Add support for the LLVM [MemTagSanitizer](https://llvm.org/docs/MemTagSanitizer.html).

On hardware which supports it (see caveats below), the MemTagSanitizer can catch bugs similar to AddressSanitizer and HardwareAddressSanitizer, but with lower overhead.

On a tag mismatch, a SIGSEGV is signaled with code SEGV_MTESERR / SEGV_MTEAERR.

# Usage

`-Zsanitizer=memtag -C target-feature="+mte"`

# Comments/Caveats

* MemTagSanitizer is only supported on AArch64 targets with hardware support
* Requires `-C target-feature="+mte"`
* LLVM MemTagSanitizer currently only performs stack tagging.

# TODO

* Tests
* Example
2022-02-18 23:23:03 +01:00
Amanieu d'Antras
11250b8661 asm: Allow the use of r8-r14 as clobbers on Thumb1
Previously these were entirely disallowed, except for r11 which was
allowed by accident.
2022-02-18 20:26:40 +00:00
bors
30b3f35c42 Auto merge of #93577 - nikic:llvm-14, r=nagisa
Upgrade to LLVM 14

LLVM patch state:
 * [x] a55727f334 Backported.
 * [x] c3c82dc124 Backported as 917c47b3bf.
 * [x] 6e8f9ab632 No plan to upstream.
 * [x] 319f4b2d52 Backported.
 * [x] 8b2c25d321 No plan to upstream.
 * [x] 75fef2efd4 No plan to upstream.
 * [ ] adef757547 Upstreamed as 2d2ef384b2. Needs backport.
 * [x] 4b7c1b4910 No plan to upstream.
 * [x] 3f5ab0c061 No plan to upstream.
 * [x] 514d05500e No plan to upstream.
 * [ ] 54c5869585 Under review at https://reviews.llvm.org/D119695 and https://reviews.llvm.org/D119856.

Release timeline:
 * LLVM 14.0.0 final planned for Mar 15.
 * Rust 1.60.0 planned for Apr 7.

Compile-time:
  * https://perf.rust-lang.org/compare.html?start=250384edc5d78533e993f38c60d64e42b21684b2&end=b87df8d2c7c5d9ac448c585de10927ab2ee1b864
  * A slight improvement on average, though no big changes either way.
  * There are some larger max-rss improvements.

r? `@ghost`
2022-02-17 13:08:46 +00:00
Nikita Popov
70ddd2ff1c Update data layout for wasm32 targets
New address spaces were added in https://reviews.llvm.org/D111154.
2022-02-16 21:15:31 +01:00
Nikita Popov
a380581ff8 Update data layout for 32-bit msvc targets
https://reviews.llvm.org/D115942 changed the alignment of f80.
2022-02-16 21:15:30 +01:00
Ivan Lozano
568aeda9e9 MemTagSanitizer Support
Adds support for the LLVM MemTagSanitizer.
2022-02-16 09:39:03 -05:00
Tomasz Miąsko
81f12eb7ef Inline Target::deref 2022-02-15 19:08:12 +01:00
Vadim Petrochenkov
da4a235c26 rustc_target: Remove compiler-rt linking hack on Android 2022-02-13 21:22:02 +08:00
bors
5c30d65683 Auto merge of #93670 - erikdesjardins:noundef, r=nikic
Apply noundef attribute to &T, &mut T, Box<T>, bool

This doesn't handle `char` because it's a bit awkward to distinguish it from `u32` at this point in codegen.

Note that this _does not_ change whether or not it is UB for `&`, `&mut`, or `Box` to point to undef. It only applies to the pointer itself, not the pointed-to memory.

Fixes (partially) #74378.

r? `@nikic` cc `@RalfJung`
2022-02-13 00:14:52 +00:00
bors
502d6aa47b Auto merge of #93854 - matthiaskrgr:rollup-bh2a85j, r=matthiaskrgr
Rollup of 7 pull requests

Successful merges:

 - #92670 (add kernel target for RustyHermit)
 - #93756 (Support custom options for LLVM build)
 - #93802 (fix oversight in the `min_const_generics` checks)
 - #93808 (Remove first headings indent)
 - #93824 (Stabilize cfg_target_has_atomic)
 - #93830 (Refactor sidebar printing code)
 - #93843 (kmc-solid: Fix wait queue manipulation errors in the `Condvar` implementation)

Failed merges:

r? `@ghost`
`@rustbot` modify labels: rollup
2022-02-10 12:31:51 +00:00