Commit Graph

234917 Commits

Author SHA1 Message Date
Philipp Krones
5eb7604482
Bump nightly version -> 2023-09-25 2023-09-25 10:26:33 +02:00
Philipp Krones
81fe8dc084
Merge remote-tracking branch 'upstream/master' into rustup 2023-09-25 10:26:11 +02:00
bors
efd04b6267 Auto merge of #3084 - RalfJung:deadcode, r=RalfJung
remove some dead code

and add a comment in the AVX test
2023-09-25 06:59:01 +00:00
Ralf Jung
085177678e remove some dead code
and add a comment in the AVX test
2023-09-25 08:56:19 +02:00
bors
d644603b80 Auto merge of #3075 - eduardosm:x86-addcarry-subborrow, r=RalfJung
Move `llvm.x86.*` shims into `shims::x86` and implement `_addcarry_u32` and `_subborrow_u{32,64}`

This PR moves all `llvm.x86.*` shims into `shims::x86` and adds `llvm.x86.addcarry.32`, `llvm.x86.subborrow.32` and `llvm.x86.subborrow.64`.

Additionally, it fixes the input carry semantics of `llvm.x86.addcarry.32`. The input carry is an 8-bit value that is interpreted as 1 when it is non-zero.

https://www.intel.com/content/www/us/en/docs/cpp-compiler/developer-guide-reference/2021-8/addcarry-u32-addcarry-u64.html
2023-09-25 06:10:43 +00:00
bors
67ad3c2394 Auto merge of #116078 - eduardosm:closure-inherit-target-feature, r=Mark-Simulacrum
Add assembly test to make sure that inlining works as expected when closures inherit target features

Closes https://github.com/rust-lang/rust/issues/108338 (the added test proves that it is working correctly)
2023-09-25 05:39:09 +00:00
Eduardo Sánchez Muñoz
4625e1e8ab Use cfg gates in x86 SSE and SSE2 tests 2023-09-25 07:18:10 +02:00
Eduardo Sánchez Muñoz
a617b89996 Implement llvm.x86.subborrow.32 and llvm.x86.subborrow.64 2023-09-25 07:18:10 +02:00
Eduardo Sánchez Muñoz
6ec63ed251 Fix the carry semantics of _addcarry_u32 and _addcarry_u64
The input carry is an 8-bit value that is interpreted as 1 when it is non-zero. The output carry is an 8-bit value that will be 0 or 1.

https://www.intel.com/content/www/us/en/docs/cpp-compiler/developer-guide-reference/2021-8/addcarry-u32-addcarry-u64.html
2023-09-25 07:18:10 +02:00
Eduardo Sánchez Muñoz
356039985e Implement llvm.x86.addcarry.32 by refactoring llvm.x86.addcarry.64 to make it generic 2023-09-25 07:18:10 +02:00
Eduardo Sánchez Muñoz
d6b30b88d0 Move llvm.x86.* implementations into shims::x86 2023-09-25 07:18:10 +02:00
Lenko Donchev
a1d181d740 Added additional visit steps to visit_generic_param() in order to avoid ICE on no bound vars. 2023-09-24 23:39:33 -05:00
bors
8c04c06317 Auto merge of #116074 - fzs111:clarify-pin-docs, r=Mark-Simulacrum
Clarify example in `Pin::new_unchecked` docs

This example in the docs of `Pin::new_unchecked` puzzled me for a relatively long time. Now I understand that it comes down to the difference between dropping the `Pin` vs dropping the pinned value.

I have extended the explanation to highlight this difference. In my opinion it is clearer now, and I hope it helps others understand `Pin` better.
2023-09-25 03:50:59 +00:00
bors
5105b1ec58 Auto merge of #116057 - RalfJung:io-safety, r=Mark-Simulacrum
fix OS-specific I/O safety docs since the io_safety feature is stable

Looks like this text was forgotten to be updated when `io_safety` got stabilized: it still says "once the io_safety feature is stable".

Also adjust the wording a bit for how these docs relate to the general concept of I/O safety.
2023-09-25 00:17:13 +00:00
bors
91958e0a74 Auto merge of #116117 - cjgillot:drop-tracking-mir-noscope, r=compiler-errors
Remove dead diagnostic code for generators

This code has become unreachable with #107421.
2023-09-24 22:25:15 +00:00
Ralf Jung
ad509633a2 ConstParamTy: require Eq 2023-09-24 23:38:07 +02:00
Ralf Jung
4f86c69184 fix ICE due to empty span and empty suggestions 2023-09-24 23:32:36 +02:00
bors
aa137a7e57 Auto merge of #11552 - jonboh:ice_threshold_0_enum_variants, r=y21
prevent ice when threshold is 0 and enum has no variants

changelog: [`enum_variant_names`]: prevent ice when threshold is 0 and enum has no variants

r? `@y21`

Fixes the same ice issue raised during review of https://github.com/rust-lang/rust-clippy/pull/11496
2023-09-24 20:58:58 +00:00
bors
37390d6563 Auto merge of #115911 - nebulark:refactor_targetmachine, r=Nilstrieb
Add OwnedTargetMachine to manage llvm:TargetMachine

LLVMRustDisposeTargetMachine taking a &mut could be undefined behaviour.
Wrapping it with a struct and using pointers instead avoids this problem.
In addition the TargetMachine is now automatically freed via the Wrappers drop impl. This should fix some memory leaks when
create_informational_target_machine was used, e.g. 327e6cf55c/compiler/rustc_codegen_llvm/src/llvm_util.rs (L291-L314)

r? `@Nilstrieb`
2023-09-24 20:36:44 +00:00
Maybe Waffle
99a2fa17e6 Add a test for printing literals via proc-macro 2023-09-24 20:24:33 +00:00
Maybe Waffle
285e574b8e Fix .to_string() of proc_macro::Literal (properly print cstr literals) 2023-09-24 20:05:27 +00:00
Jon
0433e458da
use first instead of get(0)
Co-authored-by: Timo <30553356+y21@users.noreply.github.com>
2023-09-24 21:37:56 +02:00
Florian Schmiderer
3409ca65d8 Add OwnedTargetMachine to manage llvm:TargetMachine. Uses pointers
instead of &'static mut and provides safe interface to create/dispose
it.
2023-09-24 21:11:37 +02:00
bors
a1c7a1c89f Auto merge of #116120 - GuillaumeGomez:regression-102467, r=compiler-errors
Add regression test for #102467

Fixes #102467.

r? `@compiler-errors`
2023-09-24 18:47:52 +00:00
bors
fc61fabc24 Auto merge of #116116 - Nilstrieb:gate-all-__SECRET_INTERNALS_DO_NOT_USE_OR_YOU_WILL_BE_FIRED, r=compiler-errors
Rename the legacy feature gating macro

It had a really confusing name by shadowing the previous name, which has
caused issues in the past where people added their new syntax in the
legacy location.

This makes it clear.

Also adds a comment about the return type notation gating, which confused me why it was here at first before `@compiler-errors` told me why.
2023-09-24 16:59:59 +00:00
jonboh
b3e262acfd add ui-toml test 2023-09-24 18:25:20 +02:00
bors
26eeea6a1b Auto merge of #116069 - compiler-errors:debug-tuple, r=Nilstrieb
Fix debug printing of tuple

Self-explanatory. Didn't create a UI test, but I guess I could -- not sure where debug output shows up in rustc_attrs to make a sufficient test, tho.
2023-09-24 15:16:18 +00:00
bors
94fc43121f Auto merge of #11560 - y21:ui-toml-tests, r=Alexendoo
Add missing tests for configuration options

I noticed that a lot of lints didn't have test(s) for their configuration. This leads to issues like #11481 where the lint just does nothing with it.

This PR adds tests for *almost*[^1] all of the lints with a configuration that didn't have a test in ui-toml.
The tests that I wrote here are usually two cases: one for where it's right above or under the limit set by the config where it shouldn't lint and another one for right above where it should.

changelog: none

[^1]: allow-one-hash-in-raw-strings is ignored by needless_raw_string_hashes
2023-09-24 15:09:33 +00:00
Ralf Jung
b589976606 use a must_hold variant for checking PartialEq 2023-09-24 16:59:47 +02:00
Eduardo Sánchez Muñoz
5aba8739d7 Add assembly test to make sure that inlining works as expected when closures inherit target features 2023-09-24 16:36:31 +02:00
Ralf Jung
c3ed0c454e make sure we always emit the no-PartialEq lint, even if there were other lints 2023-09-24 16:36:26 +02:00
Ralf Jung
c5fccb98ea work towards rejecting consts in patterns that do not implement PartialEq 2023-09-24 16:36:26 +02:00
y21
6e80db96ea use a smaller number in test that fits in usize for 32 bit 2023-09-24 16:29:26 +02:00
y21
6ce61d543a add missing configuration tests 2023-09-24 15:19:18 +02:00
chenx97
8e558bcf1e tidy: remove io-lifetimes from the dependency list 2023-09-24 21:11:24 +08:00
chenx97
141c4636a7 deps: update rustix and linux-raw-sys for MIPS R6
commands that perform this update:

```shell
cargo +nightly update tempfile clap
cargo +nightly update linux-raw-sys rustix
```
2023-09-24 21:11:10 +08:00
Guillaume Gomez
79f3fe48b0 Add regression test for #102467 2023-09-24 14:09:38 +02:00
bors
70a7fe1743 Auto merge of #116076 - chriswailes:android-riscv-extension-update, r=cjgillot
Add Zba, Zbb, and Zbs as target features for riscv64-linux-android

This pull request adds the Zba, Zbb, and Zbs target features to the `riscv64-linux-android` target specification.  These features have been enabled and tested internally in Android infrastructure.
2023-09-24 11:40:45 +00:00
bors
b791f02834 Auto merge of #3081 - eduardosm:avx512-tests, r=RalfJung
Put AVX512 tests together
2023-09-24 11:34:00 +00:00
Eduardo Sánchez Muñoz
413ff386c2 Put AVX512 tests together 2023-09-24 11:57:53 +02:00
bors
c7224e3c95 Auto merge of #105861 - Ayush1325:uefi-std-minimial, r=workingjubilee
Add Minimal Std implementation for UEFI

# Implemented modules:
1. alloc
2. os_str
3. env
4. math

# Related Links
Tracking Issue: https://github.com/rust-lang/rust/issues/100499
API Change Proposal: https://github.com/rust-lang/libs-team/issues/87

# Additional Information
This was originally part of https://github.com/rust-lang/rust/pull/100316. Since that PR was becoming too unwieldy and cluttered, and with suggestion from `@dvdhrm,` I have extracted a minimal std implementation to this PR.

The example in `src/doc/rustc/src/platform-support/unknown-uefi.md` has been tested for `x86_64-unknown-uefi` and `i686-unknown-uefi` in OVMF. It would be great if someone more familiar with AARCH64 can help with testing for that target.

Signed-off-by: Ayush Singh <ayushsingh1325@gmail.com>
2023-09-24 09:47:30 +00:00
Camille GILLOT
26cb34cd18 Remove span from BrAnon. 2023-09-24 09:46:55 +00:00
Camille GILLOT
b2ff77cb78 Do not clone valtree and slice constants. 2023-09-24 09:09:05 +00:00
Camille GILLOT
5f9d64d72f Embed simplification into VnState. 2023-09-24 09:09:04 +00:00
Camille GILLOT
3311536740 Workaround issue 112651. 2023-09-24 09:09:04 +00:00
Camille GILLOT
6dfa053697 Complete miri test. 2023-09-24 09:09:04 +00:00
Camille GILLOT
644e40f536 Do not assume anything about repeated reification of generic functions. 2023-09-24 09:09:04 +00:00
Camille GILLOT
db50bd96e5 Add a paragraph about the assume bitwise equal. 2023-09-24 09:09:04 +00:00
Camille GILLOT
1ea9399803 Do not check copiability. 2023-09-24 09:09:04 +00:00
Camille GILLOT
6fa55d0aff Add documentation. 2023-09-24 09:09:04 +00:00