Commit Graph

41591 Commits

Author SHA1 Message Date
许杰友 Jieyou Xu (Joe)
c112195fec
Rollup merge of #133620 - dev-ardi:simplify-hir_typeck_pass_to_variadic_function, r=compiler-errors
Simplify hir_typeck_pass_to_variadic_function

r? ``@compiler-errors``
This reworks a bit how the diagnostic is generated so that it does the same as #133538

The `help` is useless now so I removed it
2024-11-30 12:56:54 +08:00
许杰友 Jieyou Xu (Joe)
46f826cff7
Rollup merge of #133599 - esp-rs:target/esp32s2-forced-atomics, r=Amanieu
Add `+forced-atomics` feature to esp32s2 no_std  target

Similar to https://github.com/rust-lang/rust/pull/114499 but for the Xtensa backend. The ESP32-S2 doesn't have native atomic support, but can have atomic load/stores as part of the ISA with this LLVM codegen feature.

Note: The current rev of LLVM that rustc is using doesn't contain the `+forced-atomics` feature for Xtensa, but I'm pushing this now to remove the patch from our fork in `esp-rs/rust`.

r? ``@Amanieu`` because you reviewed the related RISC-V PR
2024-11-30 12:56:53 +08:00
许杰友 Jieyou Xu (Joe)
ab4588a619
Rollup merge of #133587 - taiki-e:loongarch-asm-freg, r=Amanieu
Fix target_feature handling in freg of LoongArch inline assembly

In LoongArch inline assembly, freg currently always accepts f32/f64 as input/output.

9b4d7c6a40/compiler/rustc_target/src/asm/loongarch.rs (L41)

However, these types actually require f/d target features as in RISC-V.
Otherwise, an (ugly) compile error will occur: https://godbolt.org/z/K61Gq1E9E

f32/f64 without f:

```
error: couldn't allocate output register for constraint '{$f1}'
  --> <source>:12:11
   |
12 |     asm!("", in("$f1") x, lateout("$f1") y);
   |           ^
```

f64 with f but without d:

```
error: scalar-to-vector conversion failed, possible invalid constraint for vector type
  --> <source>:19:11
   |
19 |     asm!("", in("$f1") x, lateout("$f1") y);
   |           ^
```

cc ``@heiher``

r? ``@Amanieu``

``@rustbot`` label +O-LoongArch +A-inline-assembly
2024-11-30 12:56:53 +08:00
许杰友 Jieyou Xu (Joe)
70e71f570d
Rollup merge of #133585 - estebank:issue-133563, r=jieyouxu
Do not call `extern_crate` on current trait on crate mismatch errors

When we encounter an error caused by traits/types of different versions of the same crate, filter out the current crate when collecting spans to add to the context so we don't call `extern_crate` on the `DefId` of the current crate, which is meaningless and ICEs.

Produced output with this filter:

```
error[E0277]: the trait bound `foo::Struct: Trait` is not satisfied
  --> y.rs:13:19
   |
13 |     check_trait::<foo::Struct>();
   |                   ^^^^^^^^^^^ the trait `Trait` is not implemented for `foo::Struct`
   |
note: there are multiple different versions of crate `foo` in the dependency graph
  --> y.rs:7:1
   |
4  | extern crate foo;
   | ----------------- one version of crate `foo` is used here, as a direct dependency of the current crate
5  |
6  | pub struct Struct;
   | ----------------- this type implements the required trait
7  | pub trait Trait {}
   | ^^^^^^^^^^^^^^^ this is the required trait
   |
  ::: x.rs:4:1
   |
4  | pub struct Struct;
   | ----------------- this type doesn't implement the required trait
5  | pub trait Trait {}
   | --------------- this is the found trait
   = note: two types coming from two different versions of the same crate are different types even if they look the same
   = help: you can use `cargo tree` to explore your dependency tree
note: required by a bound in `check_trait`
  --> y.rs:10:19
   |
10 | fn check_trait<T: Trait>() {}
   |                   ^^^^^ required by this bound in `check_trait`
```

Fix #133563.
2024-11-30 12:56:52 +08:00
许杰友 Jieyou Xu (Joe)
5192810868
Rollup merge of #132750 - daltenty:daltenty/libs, r=jieyouxu
[AIX] handle libunwind native_libs

AIX should follow a similar path here to other libunwind platforms, with regards to system vs in-tree libunwind and the native lib search directories.

Having the right native lib search directories here is also required to get the correct default library search paths, due to some quirks of the AIX linker.
2024-11-30 12:56:50 +08:00
许杰友 Jieyou Xu (Joe)
dd99f11ef8
Rollup merge of #116161 - Soveu:varargs2, r=cjgillot
Stabilize `extended_varargs_abi_support`

I think that is everything? If there is any documentation regarding `extern` and/or varargs to correct, let me know, some quick greps suggest that there might be none.

Tracking issue: https://github.com/rust-lang/rust/issues/100189
2024-11-30 12:56:50 +08:00
bors
1fc691e6dd Auto merge of #133533 - BoxyUwU:bump-boostrap, r=jieyouxu,Mark-Simulacrum
Bump boostrap compiler to new beta

Currently failing due to something about the const stability checks and `panic!`. I'm not sure why though since I wasn't able to see any PRs merged in the past few days that would result in a `cfg(bootstrap)` that shouldn't be removed. cc `@RalfJung` #131349
2024-11-29 22:39:10 +00:00
David Tenty
a9cb2d6709 Add a comment 2024-11-29 16:40:13 -05:00
Orion Gonzalez
ce98bf3d79 simplify how the hir_typeck_pass_to_variadic_function diagnostic is created 2024-11-29 20:49:06 +01:00
Matthias Krüger
eabe6db9b1
Rollup merge of #133592 - WaffleLapkin:misc-meowing, r=jieyouxu
Misc: better instructions for envrc, ignore `/build` instead of `build/`

See commits for more information.

r? ``@jieyouxu``
2024-11-29 16:02:24 +01:00
Matthias Krüger
6c9e922685
Rollup merge of #131323 - jfrimmel:avr-inline-asm-clobber-abi, r=Amanieu
Support `clobber_abi` in AVR inline assembly

This PR implements the `clobber_abi` part necessary to eventually stabilize the inline assembly for AVR. This is tracked in #93335.
This is heavily inspired by the sibling-PR #131310 for the MSP430. I've explained my reasoning in the first commit message in detail, which is reproduced below for easier reviewing:

This follows the [ABI documentation] of AVR-GCC:

> The [...] call-clobbered general purpose registers (GPRs) are registers that might be destroyed (clobbered) by a function call.
>
> - **R18–R27, R30, R31**
>
>   These GPRs are call clobbered. An ordinary function may use them without restoring the contents. [...]
>
> - **R0, T-Flag**
>
>   The temporary register and the T-flag in SREG are also call-clobbered, but this knowledge is not exposed explicitly to the compiler (R0 is a fixed register).

Therefore this commit lists the aforementioned registers `r18–r27`, `r30` and `r31` as clobbered registers. Since the `r0` register (listed above as well) is not available in inline assembly at all (potentially because the AVR-GCC considers it a fixed register causing the register to never be used in register allocation and LLVM adopting this), there is no need to list it in the clobber list (the `r0`-variant is not even available). A comment was added to ensure, that the `r0` gets added to the clobber-list once the register gets usable in inline ASM.
Since the SREG is normally considered clobbered anyways (unless the user supplies the `preserve_flags`-option), there is no need to explicitly list a bit in this register (which is not possible to list anyways).

Note, that this commit completely ignores the case of interrupts (that are described in the ABI-specification), since every register touched in an ISR need to be saved anyways.

[ABI documentation]: https://gcc.gnu.org/wiki/avr-gcc#Call-Used_Registers

r? ``@Amanieu``

``@rustbot`` label +O-AVR
2024-11-29 16:02:20 +01:00
bors
0c4f3a45b8 Auto merge of #133619 - matthiaskrgr:rollup-7ywaheb, r=matthiaskrgr
Rollup of 7 pull requests

Successful merges:

 - #132782 (improvements on initial sysroot and libdir finding logics)
 - #133466 (Fix typos in pin.rs)
 - #133492 (bootstrap: allow skipping steps with start of path)
 - #133501 (support revealing defined opaque post borrowck)
 - #133530 (Use consistent wording in docs, use is zero instead of is 0)
 - #133538 (Better diagnostic for fn items in variadic functions)
 - #133590 (Rename `-Zparse-only`)

r? `@ghost`
`@rustbot` modify labels: rollup
2024-11-29 12:05:41 +00:00
Matthias Krüger
ce52b7b3d8
Rollup merge of #133590 - nnethercote:rename-parse-only, r=estebank
Rename `-Zparse-only`

It's a misleading name.

r? ````@estebank````
2024-11-29 10:19:00 +01:00
Matthias Krüger
72cf40d9ed
Rollup merge of #133538 - dev-ardi:69232-better-diag, r=compiler-errors
Better diagnostic for fn items in variadic functions

closes #69232
2024-11-29 10:18:59 +01:00
Matthias Krüger
6863327ecc
Rollup merge of #133501 - lcnr:post-borrowck-analysis, r=compiler-errors
support revealing defined opaque post borrowck

By adding a new `TypingMode::PostBorrowckAnalysis`. Currently only supported with the new solver and I didn't look into the way we replace `ReErased`. ``@compiler-errors`` mentioned that always using existentials may be unsound.

r? ``@compiler-errors``
2024-11-29 10:18:57 +01:00
bors
5bbbc0938c Auto merge of #133431 - nnethercote:rm-HybridBitSet, r=Mark-Simulacrum
Remove `HybridBitSet`

`HybridBitSet` was introduced under the name `HybridIdxSetBuf` way back in #53383 where it was a big win for NLL borrow checker performance. In #93984 the more flexible `ChunkedBitSet` was added. Uses of `HybridBitSet` have gradually disappeared (e.g. #116152) and there are now few enough that they can be replaced with `BitSet` or `ChunkedBitSet`, and `HybridBitSet` can be removed, cutting more than 700 lines of code.

r? `@Mark-Simulacrum`
2024-11-29 09:03:50 +00:00
Nicholas Nethercote
4846c1922d Remove HybridBitSet.
It's no longer used.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
b7ff2aedd9 Stop using HybridBitSet in SparseBitMatrix.
Use `ChunkedBitSet` instead.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
0df6a018e1 Stop using HybridBitSet in dataflow diffs.
As part of the larger goal of reducing `HybridBitSet` use in general.
This code is for debugging only and isn't performance sensitive, so
`ChunkedBitSet` should be fine.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
346929cb80 Remove unused HybridBitSet methods from BitSetExt. 2024-11-29 17:23:34 +11:00
Nicholas Nethercote
ded4dfde19 Speed up ChunkedBitIter
The current implementation is slow because it does an operation for
every bit in the set, even zero bits. So if you have a large bitset with
many zero bits (which is common) it's very slow.

This commit improves the iterator to skip over `Zeros` chunks in a
single step, and uses the fast `BitIter` for `Mixed` chunks. It also
removes the existing `fold` implementation, which was only there because
the old iterator was slow.
2024-11-29 17:23:32 +11:00
Nicholas Nethercote
ff78002566 Tiny ChunkedBitSet improvements.
- Fix a typo in a comment.
- Remove unnecessary `Chunk::` qualifiers.
- Rename `ChunkedBitIter::bitset` as `ChunkedBitIter::bit_set`, because
  `bit_set` is the form used everywhere else.
- Avoid some unnecessary local variables.
2024-11-29 17:01:48 +11:00
Nicholas Nethercote
15b24c46b4 Clarify ChunkSize invariants.
`ChunkedBitSet::is_empty` currently does an unnecessary check. This
commit removes that check and adds clarifying comments and an assertion
that demonstrate why it's unnecessary.
2024-11-29 17:01:48 +11:00
bors
cb2bd2bb06 Auto merge of #133608 - Zalathar:spans-revert, r=jieyouxu
Revert #133418 (Store coverage source regions as `Span`) due to regression #133606

This reverts commit adf9b5fcd1, reversing changes made to af1ca153d4.

Reverting #133418 due to regressions reported at #133606.

r? jieyouxu
2024-11-29 05:38:09 +00:00
Zalathar
9461f4296f Revert "Rollup merge of #133418 - Zalathar:spans, r=jieyouxu"
This reverts commit adf9b5fcd1, reversing
changes made to af1ca153d4.

Reverting due to <https://github.com/rust-lang/rust/issues/133606>.
2024-11-29 14:57:01 +11:00
bors
d6f88291f3 Auto merge of #133409 - RalfJung:target-consistency, r=lcnr
ensure JSON-defined targets are consistent

We have a `check_consistency` check that ensures some invariants which (presumably) the rest of the compiler relies on. However, JSON targets can easily be written in a way that violates those invariants. So this PR applies the same consistency check to JSON targets that we already enforce for built-in targets.

I have converted many of the assertions in that function to new macros that show a nice error instead of a panic; if people are okay with the general approach here, I can do that for the rest of the checks as well.
2024-11-29 01:35:20 +00:00
Orion Gonzalez
1e4817cd33 bless the tests and add a new one 2024-11-29 00:45:14 +01:00
Orion Gonzalez
b36dcc1a38 Improve the diagnostic of fn item in variadic fn 2024-11-29 00:45:14 +01:00
bors
d53f0b1d8e Auto merge of #123244 - Mark-Simulacrum:share-inline-never-generics, r=saethlin
Enable -Zshare-generics for inline(never) functions

This avoids inlining cross-crate generic items when possible that are
already marked inline(never), implying that the author is not intending
for the function to be inlined by callers. As such, having a local copy
may make it easier for LLVM to optimize but mostly just adds to binary
bloat and codegen time. In practice our benchmarks indicate this is
indeed a win for larger compilations, where the extra cost in dynamic
linking to these symbols is diminished compared to the advantages in
fewer copies that need optimizing in each binary.

It might also make sense it expand this with other heuristics (e.g.,
`#[cold]`) in the future, but this seems like a good starting point.

FWIW, I expect that doing cleanup in where we make the decision
what should/shouldn't be shared is also a good idea. Way too
much code needed to be tweaked to check this. But I'm hoping
to leave that for a follow-up PR rather than blocking this on it.
2024-11-28 21:44:34 +00:00
Scott Mabin
727f6a6d13 Add +forced-atomics feature to esp32s2 2024-11-28 21:41:34 +00:00
Maybe Lapkin
8e77349782
fix a comment with uneven number of backticks in rustc_mir_build
this is funny though! apparently tidy parsed `.gitignore`, but did not
recognize unignore lines (`!...`), so tidy was ignoring `rustc_mir_build`
this whole time (at least for some lints?).
2024-11-28 21:54:27 +01:00
Nicholas Nethercote
accdfa1e52 Update -Zshow-span help message.
To clarify how it works.
2024-11-29 06:10:16 +11:00
Nicholas Nethercote
76adf05cfb Rename -Zparse-only.
I was surprised to find that running with `-Zparse-only` only parses the
crate root file. Other files aren't parsed because that happens later
during expansion.

This commit renames the option and updates the help message to make this
clearer.
2024-11-29 06:10:15 +11:00
Mark Rousskov
4a216a25d1 Share inline(never) generics across crates
This reduces code sizes and better respects programmer intent when
marking inline(never). Previously such a marking was essentially ignored
for generic functions, as we'd still inline them in remote crates.
2024-11-28 13:43:05 -05:00
Taiki Endo
0c8e36bb30 Fix target_feature handling in freg of LoongArch inline assembly 2024-11-29 03:01:33 +09:00
Esteban Küber
8574f374e2 Do not call extern_crate on current trait on crate mismatch errors
When we encounter an error caused by traits/types of different versions of the same crate, filter out the current crate when collecting spans to add to the context so we don't call `extern_crate` on the `DefId` of the current crate, which is meaningless and ICEs.

Produced output with this filter:

```
error[E0277]: the trait bound `foo::Struct: Trait` is not satisfied
  --> y.rs:13:19
   |
13 |     check_trait::<foo::Struct>();
   |                   ^^^^^^^^^^^ the trait `Trait` is not implemented for `foo::Struct`
   |
note: there are multiple different versions of crate `foo` in the dependency graph
  --> y.rs:7:1
   |
4  | extern crate foo;
   | ----------------- one version of crate `foo` is used here, as a direct dependency of the current crate
5  |
6  | pub struct Struct;
   | ----------------- this type implements the required trait
7  | pub trait Trait {}
   | ^^^^^^^^^^^^^^^ this is the required trait
   |
  ::: x.rs:4:1
   |
4  | pub struct Struct;
   | ----------------- this type doesn't implement the required trait
5  | pub trait Trait {}
   | --------------- this is the found trait
   = note: two types coming from two different versions of the same crate are different types even if they look the same
   = help: you can use `cargo tree` to explore your dependency tree
note: required by a bound in `check_trait`
  --> y.rs:10:19
   |
10 | fn check_trait<T: Trait>() {}
   |                   ^^^^^ required by this bound in `check_trait`
```

Fix #133563.
2024-11-28 17:55:52 +00:00
bors
7e565cce6a Auto merge of #133468 - lcnr:uwu4, r=BoxyUwU
always create `DefId`s for anon consts

but don't use them anywhere, we intentionally don't encode them in the crate metadata.

best reviewed by disabling whitespace.

This pretty much reimplements #133285 while adding the tests of #133455. Fixes #133064

r? `@BoxyUwU` `@compiler-errors`
2024-11-28 15:58:17 +00:00
Julian Frimmel
67d2f3f685
Reword error message of reserved AVR registers
Those are reserved as per the GCC (and thus LLVM) ABI, which is distinct from an
issue. The rewording was requested in this [review].

[review]: https://github.com/rust-lang/rust/pull/131323#issuecomment-2479178721
2024-11-28 16:12:04 +01:00
Julian Frimmel
ba73166556
Support clobber_abi for AVR inline assembly
This commit adds the relevant registers to the list of clobbered regis-
ters (part of #93335). This follows the [ABI documentation] of AVR-GCC:

> The [...] call-clobbered general purpose registers (GPRs) are
> registers that might be destroyed (clobbered) by a function call.
>
> - **R18–R27, R30, R31**
>
>   These GPRs are call clobbered. An ordinary function may use them
>   without restoring the contents. [...]
>
> - **R0, T-Flag**
>
>   The temporary register and the T-flag in SREG are also call-
>   clobbered, but this knowledge is not exposed explicitly to the
>   compiler (R0 is a fixed register).

Therefore this commit lists the aforementioned registers `r18–r27`,
`r30` and `r31` as clobbered registers. Since the `r0` register (listed
above as well) is not available in inline assembly at all (potentially
because the AVR-GCC considers it a fixed register causing the register
to never be used in register allocation and LLVM adopting this), there
is no need to list it in the clobber list (the `r0`-variant is not even
available). A comment was added to ensure, that the `r0` gets added to
the clobber-list once the register gets usable in inline ASM.
Since the SREG is normally considered clobbered anyways (unless the user
supplies the `preserve_flags`-option), there is no need to explicitly
list a bit in this register (which is not possible to list anyways).

Note, that this commit completely ignores the case of interrupts (that
are described in the ABI-specification), since every register touched in
an ISR need to be saved anyways.

[ABI documentation]: https://gcc.gnu.org/wiki/avr-gcc#Call-Used_Registers
2024-11-28 16:12:02 +01:00
lcnr
d401a078e7 update comment 2024-11-28 12:22:02 +00:00
lcnr
23ba2d1194 ast_lowering: rm separate def_id_parent
no longer necessary as we now always create a ` DefId`  for anon-consts
2024-11-28 12:22:02 +00:00
lcnr
94131bd0a8 always create DefIds when lowering anon-consts 2024-11-28 12:22:02 +00:00
Guillaume Gomez
22c5bb0bdc
Rollup merge of #133560 - clubby789:mut-mut-space, r=jieyouxu
Trim extra space in 'repeated `mut`' diagnostic

Trim an extra space when removing repeated `mut`.

Also an extra test for even more repeated `mut`s
2024-11-28 12:06:07 +01:00
Guillaume Gomez
7201f70c37
Rollup merge of #133557 - Monadic-Cat:small_doc_fixes, r=bjorn3
Small doc fixes in `rustc_codegen_ssa`

I'm trying to make a toy codegen backend for `rustc`, and I got confused for a few minutes about what `codegen_backend` was referring to in the `CodegenBackend::join_codegen` docs.

Experimentally, it looks like the result of `CodegenBackend::codegen_crate` is passed to `CodegenBackend::join_codegen`, so this updates the docs to refer to that. This time using intra-doc links to hopefully cause people to notice if that gets out of date again.

Also, added another intra-doc link nearby, on `CodegenBackend::link`, for the same reason.
2024-11-28 12:06:07 +01:00
Guillaume Gomez
ca71c8fe5e
Rollup merge of #133487 - pitaj:reserve-guarded-strings, r=fee1-dead
fix confusing diagnostic for reserved `##`

Closes #131615
2024-11-28 12:06:04 +01:00
Guillaume Gomez
23bab15d73
Rollup merge of #133463 - taiki-e:aarch64-asm-x18, r=Amanieu
Fix handling of x18 in AArch64 inline assembly on ohos/trusty or with -Zfixed-x18

Currently AArch64 inline assembly allows using x18 on ohos/trusty or with -Zfixed-x18.

7db7489f9b/compiler/rustc_target/src/asm/aarch64.rs (L74-L76)

However, x18 is reserved in these environments and should not be allowed in the input/output operands of inline assemblies as it is in Android, Windows, etc..

7db7489f9b/compiler/rustc_target/src/spec/targets/aarch64_unknown_linux_ohos.rs (L19)
7db7489f9b/compiler/rustc_target/src/spec/targets/aarch64_unknown_trusty.rs (L18)
7db7489f9b/compiler/rustc_codegen_llvm/src/llvm_util.rs (L764-L771)

(As for ohos, +reserve-x18 is [redundant](c417b7a695 (diff-0ddf23e0bf2b28b2d05f842f087d1e6f694e8e06d1765e8d0f10d47fddcdff9c)) since 7a966b9188 that starting using llvm's ohos targets. So removed it from target-spec.)

This fix may potentially break the code for tier 2 target (aarch64-unknown-linux-ohos). (As for others, aarch64-unknown-trusty is tier 3 and -Zfixed-x18 is unstable so breaking them should be fine.)
However, in any case, it seems suspicious that the code that is broken by this was sound.

r? `@Amanieu`

`@rustbot` label O-AArch64 +A-inline-assembly
2024-11-28 12:06:02 +01:00
Guillaume Gomez
470c4f94e8
Rollup merge of #133452 - taiki-e:hexagon-asm-pred, r=Amanieu
Support predicate registers (clobber-only) in Hexagon inline assembly

The result of the Hexagon instructions such as comparison, store conditional, etc. is stored in predicate registers (`p[0-3]`), but currently there is no way to mark it as clobbered in `asm!`.

This is also needed for `clobber_abi` (although implementing `clobber_abi` will require the addition of support for [several more register classes](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp#L71-L90). see also https://github.com/rust-lang/rust/issues/93335#issuecomment-2395210055).

Refs:
- [Section 6 "Conditional Execution" in Qualcomm Hexagon V73 Programmer’s Reference Manual](https://docs.qualcomm.com/bundle/publicresource/80-N2040-53_REV_AB_Qualcomm_Hexagon_V73_Programmers_Reference_Manual.pdf#page=90)
- [Register definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td#L155)

cc `@androm3da` (target maintainer of hexagon-unknown-{[none-elf](https://doc.rust-lang.org/nightly/rustc/platform-support/hexagon-unknown-none-elf.html#target-maintainers),[linux-musl](https://doc.rust-lang.org/nightly/rustc/platform-support/hexagon-unknown-linux-musl.html#target-maintainers)})

r? `@Amanieu`

`@rustbot` label +A-inline-assembly
(Currently there is no O-hexagon label...)
2024-11-28 12:06:02 +01:00
Guillaume Gomez
89ae19ee0d
Rollup merge of #133422 - taiki-e:riscv-e-clobber-abi, r=Amanieu
Fix clobber_abi in RV32E and RV64E inline assembly

Currently clobber_abi in RV32E and RV64E inline assembly is implemented using InlineAsmClobberAbi::RiscV, but broken since x16-x31 cannot be used in RV32E and RV64E.

```
error: cannot use register `x16`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x17`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x28`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x29`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x30`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^

error: cannot use register `x31`: register can't be used with the `e` target feature
  --> <source>:42:14
   |
42 |     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
   |              ^^^^^^^^^^^^^^^^
```

r? `@Amanieu`

`@rustbot` label O-riscv +A-inline-assembly
2024-11-28 12:06:01 +01:00
Guillaume Gomez
bda2851826
Rollup merge of #133358 - compiler-errors:pin-coerce, r=eholk
Don't type error if we fail to coerce `Pin<T>` because it doesnt contain a ref

Fixes https://github.com/rust-lang/rust/issues/133222. Also moves some tests into a directory for better bookkeeping.

r? eholk or re-roll
2024-11-28 12:06:00 +01:00
lcnr
34a8c2dbba support revealing defined opaque post borrowck 2024-11-28 10:40:58 +01:00