Commit Graph

1251 Commits

Author SHA1 Message Date
Augie Fackler
72e22554ca cleanup: remove support for 3DNow! cpu features
In llvm/llvm-project@f0eb5587ce all
support for 3DNow! intrinsics and instructions were removed. Per the commit message
there, only AMD chips between 1998 and 2011 or so actually supported
these instructions, and they were effectively replaced by SSE which was
available on many more chips. I'd be very surprised if anyone had ever
used these from Rust.
2024-07-17 11:45:02 -04:00
bors
adeb79d3f5 Auto merge of #127265 - harmou01:dev/harmou01/target-spec-metadata, r=Nilstrieb
Fill out target-spec metadata for all targets

**What does this PR try to resolve?**

This PR completes the target-spec metadata fields for all targets. This is required for a corresponding Cargo PR which adds a check for whether a target supports building the standard library when the `-Zbuild-std=std` flag is passed ([see this issue](https://github.com/rust-lang/wg-cargo-std-aware/issues/87). This functionality in Cargo is reliant on the output of `--print=target-spec-json`.

**How should we test and review this PR?**

Check that a given target-spec metadata has been updated with:
```
$ ./x.py build library/std
$ build/host/stage1/bin/rustc --print=target-spec-json --target <target_name> -Zunstable-options
```

**Additional Information**

A few things to note:
* Where a targets 'std' or 'host tools' support is listed as '?' in the rust docs, these are left as 'None' with this PR. The corresponding changes in cargo will only reject an attempt to build std if the 'std' field is 'Some(false)'. In the case it is 'None', cargo will continue trying to build
* There's no rush for this to be merged. I understand that the format for this is not finalised yet.
* Related: #120745
2024-07-15 08:37:39 +00:00
sayantn
1fd0311eab Added the xop target feature and xop_target_feature gate 2024-07-12 23:30:22 +05:30
sayantn
ec05c4ea3f Add the feature gate and target-features 2024-07-11 19:00:49 -07:00
Nikita Popov
8a50bcbdce Remove extern "wasm" ABI
Remove the unstable `extern "wasm"` ABI (`wasm_abi` feature tracked
in #83788).

As discussed in https://github.com/rust-lang/rust/pull/127513#issuecomment-2220410679
and following, this ABI is a failed experiment that did not end
up being used for anything. Keeping support for this ABI in LLVM 19
would require us to switch wasm targets to the `experimental-mv`
ABI, which we do not want to do.

It should be noted that `Abi::Wasm` was internally used for two
things: The `-Z wasm-c-abi=legacy` ABI that is still used by
default on some wasm targets, and the `extern "wasm"` ABI. Despite
both being `Abi::Wasm` internally, they were not the same. An
explicit `extern "wasm"` additionally enabled the `+multivalue`
feature.

I've opted to remove `Abi::Wasm` in this patch entirely, instead
of keeping it as an ABI with only internal usage. Both
`-Z wasm-c-abi` variants are now treated as part of the normal
C ABI, just with different different treatment in
adjust_for_foreign_abi.
2024-07-11 12:20:26 +02:00
Harry Moulton
3b14526cea Fill out target-spec metadata for all targets
Complete the metadata fields for all targets. Cargo will depend on this
for checking whether a given target supports building the standard
library.
2024-07-03 10:13:07 +01:00
DianQK
c453dcd62a
Use the aligned size for alloca at args when the pass mode is cast.
The `load` and `store` instructions in LLVM access the aligned size.
2024-07-02 06:33:35 +08:00
John Paul Adrian Glaubitz
e57bbb3779 rustc_target: Build sparc_unknown_linux_gnu with -mcpu=v9 and -m32
The previously -mv8plus parameter is supported by GCC only, so let's
use something that the SPARC backend in LLVM supports as well.
2024-06-24 17:58:21 +02:00
John Paul Adrian Glaubitz
a194f42d21 rustc_target: Rewrite sparc_unknown_linux_gnu spec to use TargetOptions 2024-06-24 17:57:59 +02:00
Matthias Krüger
3108dfaced
Rollup merge of #126849 - workingjubilee:correctly-classify-arm-low-dregs, r=Amanieu
Fix 32-bit Arm reg classes by hierarchically sorting them

We were rejecting legal `asm!` because we were asking for the "greatest" feature that includes a register class, instead of the "least" feature that includes a register class. This was only revealed on certain 32-bit Arm targets because not all have the same register limitations.

This is a somewhat hacky solution, but other solutions would require potentially rearchitecting how the internals of parsing or rejecting register classes work for all targets.

Fixes #126797

r​? ``@Amanieu``
2024-06-24 06:27:16 +02:00
Jubilee Young
7c0b5cf99f compiler: Add FramePointer::ratchet 2024-06-23 00:36:33 -07:00
Jubilee Young
0d8f734172 compiler: Fix arm32 asm issues by hierarchically sorting reg classes 2024-06-22 21:39:58 -07:00
Guillaume Gomez
07e8b3ac01
Rollup merge of #126555 - beetrees:f16-inline-asm-arm, r=Amanieu
Add `f16` inline ASM support for 32-bit ARM

Adds `f16` inline ASM support for 32-bit ARM. SIMD vector types are taken from [here](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A32]).`

Relevant issue: #125398
Tracking issue: #116909

`@rustbot` label +F-f16_and_f128
2024-06-22 12:57:18 +02:00
Jubilee
e7956cd994
Rollup merge of #126530 - beetrees:f16-inline-asm-riscv, r=Amanieu
Add `f16` inline ASM support for RISC-V

This PR adds `f16` inline ASM support for RISC-V. A `FIXME` is left for `f128` support as LLVM does not support the required `Q` (Quad-Precision Floating-Point) extension yet.

Relevant issue: #125398
Tracking issue: #116909

`@rustbot` label +F-f16_and_f128
2024-06-21 21:02:26 -07:00
beetrees
771e44ebd3
Add f16 inline ASM support for RISC-V 2024-06-21 18:48:20 +01:00
beetrees
753fb070bb
Add f16 inline ASM support for 32-bit ARM 2024-06-21 18:26:42 +01:00
Matthias Krüger
2b7f6e274e
Rollup merge of #126617 - sayantn:veorq, r=workingjubilee
Expand `avx512_target_feature` to include VEX variants

Added 5 new target features for x86:

 - `AVX-IFMA`
 - `AVX-NE-CONVERT`
 - `AVX-VNNI`
 - `AVX-VNNI_INT8`
 - `AVX-VNNI_INT16`

Both LLVM and GCC already have support for these.

See also the [stdarch PR](https://github.com/rust-lang/stdarch/pull/1586)
2024-06-21 09:12:35 +02:00
Matthias Krüger
ef2e8bfcbf
Rollup merge of #126717 - nnethercote:rustfmt-use-pre-cleanups, r=jieyouxu
Clean up some comments near `use` declarations

#125443 will reformat all `use` declarations in the repository. There are a few edge cases involving comments on `use` declarations that require care. This PR cleans up some clumsy comment cases, taking us a step closer to #125443 being able to merge.

r? ``@lqd``
2024-06-20 14:07:04 +02:00
Matthias Krüger
586154b946
Rollup merge of #126380 - SergioGasquez:feat/std-xtensa, r=davidtwco
Add std Xtensa targets support

Adds std Xtensa targets. This enables using Rust on ESP32, ESP32-S2 and ESP32-S3 chips.

Tier 3 policy:

> A tier 3 target must have a designated developer or developers (the "target maintainers") on
record to be CCed when issues arise regarding the target. (The mechanism to track and CC such
developers may evolve over time.)

`@MabezDev,` `@ivmarkov` and I (`@SergioGasquez)` will maintain the targets.

> Targets must use naming consistent with any existing targets; for instance, a target for the same
CPU or OS as an existing Rust target should use the same name for that CPU or OS. Targets should
normally use the same names and naming conventions as used elsewhere in the broader ecosystem beyond
Rust (such as in other toolchains), unless they have a very good reason to diverge. Changing the
name of a target can be highly disruptive, especially once the target reaches a higher tier, so
getting the name right is important even for a tier 3 target.

The target triple is consistent with other targets.

> Target names should not introduce undue confusion or ambiguity unless absolutely necessary to
maintain ecosystem compatibility. For example, if the name of the target makes people extremely
likely to form incorrect beliefs about what it targets, the name should be changed or augmented to
disambiguate it.
> If possible, use only letters, numbers, dashes and underscores for the name. Periods (.) are known
to cause issues in Cargo.

We follow the same naming convention as other targets.

> Tier 3 targets may have unusual requirements to build or use, but must not create legal issues or
impose onerous legal terms for the Rust project or for Rust developers or users.

The target does not introduce any legal issues.

> The target must not introduce license incompatibilities.

There are no license incompatibilities

> Anything added to the Rust repository must be under the standard Rust license (MIT OR Apache-2.0).
Everything added is under that licenses

> The target must not cause the Rust tools or libraries built for any other host (even when
supporting cross-compilation to the target) to depend on any new dependency less permissive than the
Rust licensing policy. This applies whether the dependency is a Rust crate that would require adding
new license exceptions (as specified by the tidy tool in the rust-lang/rust repository), or whether
the dependency is a native library or binary. In other words, the introduction of the target must
not cause a user installing or running a version of Rust or the Rust tools to be subject to any new
license requirements.

Requirements are not changed for any other target.

> Compiling, linking, and emitting functional binaries, libraries, or other code for the target
(whether hosted on the target itself or cross-compiling from another target) must not depend on
proprietary (non-FOSS) libraries. Host tools built for the target itself may depend on the ordinary
runtime libraries supplied by the platform and commonly used by other applications built for the
target, but those libraries must not be required for code generation for the target;
cross-compilation to the target must not require such libraries at all. For instance, rustc built
for the target may depend on a common proprietary C runtime library or console output library, but
must not depend on a proprietary code generation library or code optimization library. Rust's
license permits such combinations, but the Rust project has no interest in maintaining such
combinations within the scope of Rust itself, even at tier 3.

The linker used by the targets is the GCC linker from the GCC toolchain cross-compiled for Xtensa.
GNU GPL.

> "onerous" here is an intentionally subjective term. At a minimum, "onerous" legal/licensing terms
include but are not limited to: non-disclosure requirements, non-compete requirements, contributor
license agreements (CLAs) or equivalent, "non-commercial"/"research-only"/etc terms, requirements
conditional on the employer or employment of any particular Rust developers, revocable terms, any
requirements that create liability for the Rust project or its developers or users, or any
requirements that adversely affect the livelihood or prospects of the Rust project or its developers
or users.

No such terms exist for this target

> Neither this policy nor any decisions made regarding targets shall create any binding agreement or
estoppel by any party. If any member of an approving Rust team serves as one of the maintainers of a
target, or has any legal or employment requirement (explicit or implicit) that might affect their
decisions regarding a target, they must recuse themselves from any approval decisions regarding the
target's tier status, though they may otherwise participate in discussions.

> This requirement does not prevent part or all of this policy from being cited in an explicit
contract or work agreement (e.g. to implement or maintain support for a target). This requirement
exists to ensure that a developer or team responsible for reviewing and approving a target does not
face any legal threats or obligations that would prevent them from freely exercising their judgment
in such approval, even if such judgment involves subjective matters or goes beyond the letter of
these requirements.

Understood

> Tier 3 targets should attempt to implement as much of the standard libraries as possible and
appropriate (core for most targets, alloc for targets that can support dynamic memory allocation,
std for targets with an operating system or equivalent layer of system-provided functionality), but
may leave some code unimplemented (either unavailable or stubbed out as appropriate), whether
because the target makes it impossible to implement or challenging to implement. The authors of pull
requests are not obligated to avoid calling any portions of the standard library on the basis of a
tier 3 target not implementing those portions.

The targets implement libStd almost in its entirety, except for the missing support for process, as
this is a bare metal platform. The process `sys\unix` module is currently stubbed to return "not
implemented" errors.

> The target must provide documentation for the Rust community explaining how to build for the
target, using cross-compilation if possible. If the target supports running binaries, or running
tests (even if they do not pass), the documentation must explain how to run such binaries or tests
for the target, using emulation if possible or dedicated hardware if necessary.

Here is how to build for the target https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html
and it also covers how to run binaries on the target.

> Tier 3 targets must not impose burden on the authors of pull requests, or other developers in the
community, to maintain the target. In particular, do not post comments (automated or manual) on a PR
that derail or suggest a block on the PR based on a tier 3 target. Do not send automated messages or
notifications (via any medium, including via `@)` to a PR author or others involved with a PR
regarding a tier 3 target, unless they have opted into such messages.

> Backlinks such as those generated by the issue/PR tracker when linking to an issue or PR are not
considered a violation of this policy, within reason. However, such messages (even on a separate
repository) must not generate notifications to anyone involved with a PR who has not requested such
notifications.

Understood

> Patches adding or updating tier 3 targets must not break any existing tier 2 or tier 1 target, and
must not knowingly break another tier 3 target without approval of either the compiler team or the
maintainers of the other tier 3 target.

> In particular, this may come up when working on closely related targets, such as variations of the
same architecture with different features. Avoid introducing unconditional uses of features that
another variation of the target may not have; use conditional compilation or runtime detection, as
appropriate, to let each target run code supported by that target.

No other targets should be affected

> Tier 3 targets must be able to produce assembly using at least one of rustc's supported backends
from any host target.

It can produce assembly, but it requires a custom LLVM with Xtensa support
(https://github.com/espressif/llvm-project/). The patches are trying to be upstreamed
(https://github.com/espressif/llvm-project/issues/4)
2024-06-20 14:07:01 +02:00
Nicholas Nethercote
09006d6a88 Convert some module-level // and /// comments to //!.
This makes their intent and expected location clearer. We see some
examples where these comments were not clearly separate from `use`
declarations, which made it hard to understand what the comment is
describing.
2024-06-20 09:23:18 +10:00
Sayantan Chakraborty
b6d20d1a1f Add the target-features 2024-06-19 11:19:23 +05:30
bjorn3
efa213afad Add i686-unknown-redox target
Co-Authored-By: Jeremy Soller <jackpot51@gmail.com>
2024-06-16 12:56:48 +00:00
Jeremy Soller
60a972db83 Several fixes to the redox target specs
* Allow crt-static for dylibs
* Pass -lgcc to the linker
2024-06-16 12:56:24 +00:00
beetrees
dfc5514527
Add f16 and f128 inline ASM support for x86 and x86-64 2024-06-13 16:12:23 +01:00
Sergio Gasquez
3954b744cc feat: Add std Xtensa targets support 2024-06-13 09:22:21 +02:00
Michael Goulet
754b26d882
Rollup merge of #126324 - zmodem:loongarch, r=nikic
Adjust LoongArch64 data layouts for LLVM update

The data layout was changed in LLVM 19: llvm/llvm-project#93814
2024-06-12 14:26:28 -04:00
Michael Goulet
7133257d4f
Rollup merge of #125869 - alexcrichton:add-p1-to-wasi-targets, r=wesleywiser
Add `target_env = "p1"` to the `wasm32-wasip1` target

This commit sets the `target_env` key for the
`wasm32-wasi{,p1,p1-threads}` targets to the string `"p1"`. This mirrors how the `wasm32-wasip2` target has `target_env = "p2"`. The intention of this is to more easily detect each target in downstream crates to enable adding custom code per-target.

cc #125803

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2024-06-12 14:26:24 -04:00
bors
0285dab54f Auto merge of #125141 - SergioGasquez:feat/no_std-xtensa, r=davidtwco
Add no_std Xtensa targets support

Adds no_std Xtensa targets. This enables using Rust on ESP32, ESP32-S2 and ESP32-S3 chips.

Tier 3 policy:

> A tier 3 target must have a designated developer or developers (the "target maintainers") on record to be CCed when issues arise regarding the target. (The mechanism to track and CC such developers may evolve over time.)

`@MabezDev` and I (`@SergioGasquez)` will maintain the targets.

> Targets must use naming consistent with any existing targets; for instance, a target for the same CPU or OS as an existing Rust target should use the same name for that CPU or OS. Targets should normally use the same names and naming conventions as used elsewhere in the broader ecosystem beyond Rust (such as in other toolchains), unless they have a very good reason to diverge. Changing the name of a target can be highly disruptive, especially once the target reaches a higher tier, so getting the name right is important even for a tier 3 target.

The target triple is consistent with other targets.

> Target names should not introduce undue confusion or ambiguity unless absolutely necessary to maintain ecosystem compatibility. For example, if the name of the target makes people extremely likely to form incorrect beliefs about what it targets, the name should be changed or augmented to disambiguate it.
> If possible, use only letters, numbers, dashes and underscores for the name. Periods (.) are known to cause issues in Cargo.

We follow the same naming convention as other targets.

> Tier 3 targets may have unusual requirements to build or use, but must not create legal issues or impose onerous legal terms for the Rust project or for Rust developers or users.

The target does not introduce any legal issues.

> The target must not introduce license incompatibilities.

There are no license incompatibilities

> Anything added to the Rust repository must be under the standard Rust license (MIT OR Apache-2.0).

Everything added is under that licenses

> The target must not cause the Rust tools or libraries built for any other host (even when supporting cross-compilation to the target) to depend on any new dependency less permissive than the Rust licensing policy. This applies whether the dependency is a Rust crate that would require adding new license exceptions (as specified by the tidy tool in the rust-lang/rust repository), or whether the dependency is a native library or binary. In other words, the introduction of the target must not cause a user installing or running a version of Rust or the Rust tools to be subject to any new license requirements.

Requirements are not changed for any other target.

> Compiling, linking, and emitting functional binaries, libraries, or other code for the target (whether hosted on the target itself or cross-compiling from another target) must not depend on proprietary (non-FOSS) libraries. Host tools built for the target itself may depend on the ordinary runtime libraries supplied by the platform and commonly used by other applications built for the target, but those libraries must not be required for code generation for the target; cross-compilation to the target must not require such libraries at all. For instance, rustc built for the target may depend on a common proprietary C runtime library or console output library, but must not depend on a proprietary code generation library or code optimization library. Rust's license permits such combinations, but the Rust project has no interest in maintaining such combinations within the scope of Rust itself, even at tier 3.

The linker used by the targets is the GCC linker from the GCC toolchain cross-compiled for Xtensa. GNU GPL.

> "onerous" here is an intentionally subjective term. At a minimum, "onerous" legal/licensing terms include but are not limited to: non-disclosure requirements, non-compete requirements, contributor license agreements (CLAs) or equivalent, "non-commercial"/"research-only"/etc terms, requirements conditional on the employer or employment of any particular Rust developers, revocable terms, any requirements that create liability for the Rust project or its developers or users, or any requirements that adversely affect the livelihood or prospects of the Rust project or its developers or users.

No such terms exist for this target

> Neither this policy nor any decisions made regarding targets shall create any binding agreement or estoppel by any party. If any member of an approving Rust team serves as one of the maintainers of a target, or has any legal or employment requirement (explicit or implicit) that might affect their decisions regarding a target, they must recuse themselves from any approval decisions regarding the target's tier status, though they may otherwise participate in discussions.

> This requirement does not prevent part or all of this policy from being cited in an explicit contract or work agreement (e.g. to implement or maintain support for a target). This requirement exists to ensure that a developer or team responsible for reviewing and approving a target does not face any legal threats or obligations that would prevent them from freely exercising their judgment in such approval, even if such judgment involves subjective matters or goes beyond the letter of these requirements.

Understood

> Tier 3 targets should attempt to implement as much of the standard libraries as possible and appropriate (core for most targets, alloc for targets that can support dynamic memory allocation, std for targets with an operating system or equivalent layer of system-provided functionality), but may leave some code unimplemented (either unavailable or stubbed out as appropriate), whether because the target makes it impossible to implement or challenging to implement. The authors of pull requests are not obligated to avoid calling any portions of the standard library on the basis of a tier 3 target not implementing those portions.

The target already implements core.

> The target must provide documentation for the Rust community explaining how to build for the target, using cross-compilation if possible. If the target supports running binaries, or running tests (even if they do not pass), the documentation must explain how to run such binaries or tests for the target, using emulation if possible or dedicated hardware if necessary.

Here is how to build for the target https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html and it also covers how to run binaries on the target.

> Tier 3 targets must not impose burden on the authors of pull requests, or other developers in the community, to maintain the target. In particular, do not post comments (automated or manual) on a PR that derail or suggest a block on the PR based on a tier 3 target. Do not send automated messages or notifications (via any medium, including via `@)` to a PR author or others involved with a PR regarding a tier 3 target, unless they have opted into such messages.

> Backlinks such as those generated by the issue/PR tracker when linking to an issue or PR are not considered a violation of this policy, within reason. However, such messages (even on a separate repository) must not generate notifications to anyone involved with a PR who has not requested such notifications.

Understood

> Patches adding or updating tier 3 targets must not break any existing tier 2 or tier 1 target, and must not knowingly break another tier 3 target without approval of either the compiler team or the maintainers of the other tier 3 target.

> In particular, this may come up when working on closely related targets, such as variations of the same architecture with different features. Avoid introducing unconditional uses of features that another variation of the target may not have; use conditional compilation or runtime detection, as appropriate, to let each target run code supported by that target.

No other targets should be affected

> Tier 3 targets must be able to produce assembly using at least one of rustc's supported backends from any host target.

It can produce assembly, but it requires a custom LLVM with Xtensa support (https://github.com/espressif/llvm-project/). The patches are trying to be upstreamed (https://github.com/espressif/llvm-project/issues/4)
2024-06-12 13:43:31 +00:00
Jubilee
322af5c274
Rollup merge of #125980 - kjetilkjeka:nvptx_remove_direct_passmode, r=davidtwco
Nvptx remove direct passmode

This PR does what should have been done in #117671. That is fully avoid using the `PassMode::Direct` for `extern "C" fn` for `nvptx64-nvidia-cuda` and enable the compatibility test. `@RalfJung` [pointed me in the right direction](https://github.com/rust-lang/rust/issues/117480#issuecomment-2137712501) for solving this issue.

There are still some ABI bugs after this PR is merged. These ABI tests are created based on what is actually correct, and since they continue passing with even more of them enabled things are improving. I don't have the time to tackle all the remaining issues right now, but I think getting these improvements merged is very valuable in themselves and plan to tackle more of them long term.

This also doesn't remove the use of `PassMode::Direct` for `extern "ptx-kernel" fn`. This was also not trivial to make work. And since the ABI is hidden behind an unstable feature it's less urgent.

I don't know if it's correct to request `@RalfJung` as a reviewer (due to team structures), but he helped me a lot to figure out this stuff. If that's not appropriate then `@davidtwco` would be a good candidate since he know about this topic from #117671

r​? `@RalfJung`
2024-06-12 03:57:20 -07:00
Hans Wennborg
4a06a5bc7a Adjust LoongArch64 data layouts for LLVM update
The data layout was changed in LLVM 19: llvm/llvm-project#93814
2024-06-12 12:39:09 +02:00
Ralf Jung
eb584a23bf offset_of: allow (unstably) taking the offset of slice tail fields 2024-06-08 18:17:55 +02:00
Nilstrieb
b4c439c3de Improve naming and path operations in crate loader
Simplify the path operation with `join`, clarify some of the names.
2024-06-06 21:53:29 +02:00
Alex Crichton
87ad80a638 Add target_env = "p1" to the wasm32-wasip1 target
This commit sets the `target_env` key for the
`wasm32-wasi{,p1,p1-threads}` targets to the string `"p1"`. This mirrors
how the `wasm32-wasip2` target has `target_env = "p2"`. The intention of
this is to more easily detect each target in downstream crates to enable
adding custom code per-target.

cc #125803
2024-06-01 13:04:16 -07:00
Kjetil Kjeka
14348d9519 NVPTX: Avoid PassMode::Direct for C ABI 2024-05-31 22:45:27 +02:00
Sergio Gasquez
11f70d78f5 Add no_std Xtensa targets support 2024-05-29 13:48:11 +01:00
Scott Mabin
e823288c35 Teach rustc about the Xtensa call ABI. 2024-05-29 13:48:03 +01:00
Matthias Krüger
713c852a2f
Rollup merge of #117671 - kjetilkjeka:nvptx_c_abi_avoid_direct, r=davidtwco
NVPTX: Avoid PassMode::Direct for args in C abi

Fixes #117480

I must admit that I'm confused about `PassMode` altogether, is there a good sum-up threads for this anywhere? I'm especially confused about how "indirect" and "byval" goes together. To me it seems like "indirect" basically means "use a indirection through a pointer", while "byval" basically means "do not use indirection through a pointer".

The return used to keep `PassMode::Direct` for small aggregates. It turns out that `make_indirect` messes up the tests and one way to fix it is to keep `PassMode::Direct` for all aggregates. I have mostly seen this PassMode mentioned for args. Is it also a problem for returns? When experimenting with `byval` as an alternative i ran into [this assert](61a3eea804/compiler/rustc_codegen_llvm/src/abi.rs (L463C22-L463C22))

I have added tests for the same kind of types that is already tested for the "ptx-kernel" abi. The tests cannot be enabled until something like #117458 is completed and merged.

CC: ``@RalfJung`` since you seem to be the expert on this and have already helped me out tremendously

CC: ``@RDambrosio016`` in case this influence your work on `rustc_codegen_nvvm`

``@rustbot`` label +O-NVPTX
2024-05-28 18:04:31 +02:00
Hans Wennborg
3fe3157858 Stop using the avx512er and avx512pf x86 target features
They are no longer supported by LLVM 19.

Fixes #125492
2024-05-24 20:12:42 +02:00
bors
506512391b Auto merge of #124676 - djkoloski:relax_multiple_sanitizers, r=cuviper,rcvalle
Relax restrictions on multiple sanitizers

Most combinations of LLVM sanitizers are legal-enough to enable simultaneously. This change will allow simultaneously enabling ASAN and shadow call stacks on supported platforms.

I used this python script to generate the mutually-exclusive sanitizer combinations:

```python
#!/usr/bin/python3

import subprocess

flags = [
    ["-fsanitize=address"],
    ["-fsanitize=leak"],
    ["-fsanitize=memory"],
    ["-fsanitize=thread"],
    ["-fsanitize=hwaddress"],
    ["-fsanitize=cfi", "-flto", "-fvisibility=hidden"],
    ["-fsanitize=memtag", "--target=aarch64-linux-android", "-march=armv8a+memtag"],
    ["-fsanitize=shadow-call-stack"],
    ["-fsanitize=kcfi", "-flto", "-fvisibility=hidden"],
    ["-fsanitize=kernel-address"],
    ["-fsanitize=safe-stack"],
    ["-fsanitize=dataflow"],
]

for i in range(len(flags)):
    for j in range(i):
        command = ["clang++"] + flags[i] + flags[j] + ["-o", "main.o", "-c", "main.cpp"]
        completed = subprocess.run(command, stderr=subprocess.DEVNULL)
        if completed.returncode != 0:
            first = flags[i][0][11:].replace('-', '').upper()
            second = flags[j][0][11:].replace('-', '').upper()
            print(f"(SanitizerSet::{first}, SanitizerSet::{second}),")
```
2024-05-21 15:35:29 +00:00
Matthias Krüger
4a4883bfb7
Rollup merge of #124772 - madsmtm:apple-platform-support-docs, r=oli-obk
Refactor documentation for Apple targets

Refactor the documentation for Apple targets in `rustc`'s platform support page to make it clear what the supported OS version is and which environment variables are being read (`*_DEPLOYMENT_TARGET` and `SDKROOT`). This fixes https://github.com/rust-lang/rust/issues/124215.

Note that I've expanded the `aarch64-apple-ios-sim` maintainers `@badboy` and `@deg4uss3r` to include being maintainer of all `*-apple-ios-*` targets. If you do not wish to be so, please state that, then I'll explicitly note that in the docs.

Additionally, I've added myself as co-maintainer of most of these targets.

r? `@thomcc`

I think the documentation you've previously written on tvOS is great, have mostly modified it to have a more consistent formatting with the rest of the Apple target.

I recognize that there's quite a few changes here, feel free to ask about any of them!

---

CC `@simlay` `@Nilstrieb`

`@rustbot` label O-apple
2024-05-21 12:47:04 +02:00
David Koloski
1e1143c491 Add source for mutually-exclusive list 2024-05-17 23:29:25 +00:00
Rémy Rakic
7695e5aeb4 enable rust-lld on x86_64-unknown-linux-gnu when requested
the `rust.lld` config enables rustc's `CFG_USE_SELF_CONTAINED_LINKER` env var, and we:
- set the linker-flavor to use lld
- enable the self-contained linker

this makes the target use the rust-lld linker by default
2024-05-16 16:08:06 +00:00
Michał Kostrubiec
257d222e4b Improved the documentation of the FnAbi struct 2024-05-15 20:32:27 +02:00
David Koloski
1b934f3e8c Sort mutually-exclusive pairs, update fixed tests 2024-05-15 15:40:52 +00:00
David Koloski
d7d3bd1221 Relax restrictions on multiple sanitizers
Most combinations of LLVM sanitizers are legal-enough to enable
simultaneously. This change will allow simultaneously enabling ASAN and
shadow call stacks on supported platforms.
2024-05-15 15:40:52 +00:00
Federico Maria Morrone
a3ef01b1fc
Add x86_64-unknown-linux-none target 2024-05-11 21:37:23 +02:00
bors
2259028a70 Auto merge of #124762 - madsmtm:refactor-apple-target-abi, r=lcnr,BlackHoleFox
Refactor Apple `target_abi`

This was bundled together with `Arch`, which complicated a few code paths and meant we had to do more string matching than necessary.

CC `@BlackHoleFox` as you've worked on the Apple target spec before

Related: Is there a reason why `Target`/`TargetOptions` use `StaticCow` for so many things, instead of an enum with defined values (and perhaps a catch-all case for custom target json files)? Tagging `@Nilstrieb,` as you might know?
2024-05-11 08:32:35 +00:00
许杰友 Jieyou Xu (Joe)
150633eea2
Rollup merge of #124233 - mati865:fix-support-for-upcoming-mingw-w64, r=petrochenkov
Add `-lmingwex` second time in `mingw_libs`

Upcoming mingw-w64 releases will contain small math functions refactor which moved implementation around. As a result functions like `lgamma`
now depend on libraries in this order:
`libmingwex.a` -> `libmsvcrt.a` -> `libmingwex.a`.

Fixes #124221
2024-05-11 01:15:08 +01:00
Kjetil Kjeka
ead02ba0f1 NVPTX: Avoid PassMode::Direct for args in C abi 2024-05-10 18:39:05 +02:00
Matthias Krüger
1ae0d90b72
Rollup merge of #124797 - beetrees:primitive-float, r=davidtwco
Refactor float `Primitive`s to a separate `Float` type

Now there are 4 of them, it makes sense to refactor `F16`, `F32`, `F64` and `F128` out of `Primitive` and into a separate `Float` type (like integers already are). This allows patterns like `F16 | F32 | F64 | F128` to be simplified into `Float(_)`, and is consistent with `ty::FloatTy`.

As a side effect, this PR also makes the `Ty::primitive_size` method work with `f16` and `f128`.

Tracking issue: #116909

`@rustbot` label +F-f16_and_f128
2024-05-10 16:10:46 +02:00