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5ce865e1c4
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5 Commits

Author SHA1 Message Date
gnzlbg
5ce865e1c4
Add wasm32 simd128 target feature 2018-08-08 01:39:52 +02:00
Irina Popa
077be49bde rustc_llvm: move to rustc_codegen_llvm::llvm. 2018-07-30 18:03:50 +03:00
Paolo Teti
580f437ff2 ARM: expose rclass and dsp target features 
- `dsp`: the subtarget supports the DSP (saturating arith. and such)
         instructions
- `rclass`: target is a Cortex-R

Both features are useful to support ARM MCUs on `coresimd`.

Note: Cortex-R52 is the first Armv8-R with `neon` support
 2018-07-25 09:27:55 +02:00
Jorge Aparicio
b7047bb89f ARM: expose the "mclass" target feature 2018-07-06 18:28:38 -05:00
Irina Popa
b63d7e2b1c Rename trans to codegen everywhere. 2018-05-17 15:08:30 +03:00