Commit Graph

189 Commits

Author SHA1 Message Date
Matthias Krüger
b1d059fc2b
Rollup merge of #132457 - taiki-e:needless-feature, r=workingjubilee
Remove needless #![feature(asm_experimental_arch)] from loongarch64 inline assembly test

inline assembly is already stable on this architecture.
2024-11-02 08:33:13 +01:00
Taiki Endo
57673dd646 Remove needless #![feature(asm_experimental_arch)] from loongarch64 inline assembly test 2024-11-01 22:39:08 +09:00
Taiki Endo
96e7eaf478 Move remaining inline assembly test files into asm directory 2024-11-01 22:12:55 +09:00
许杰友 Jieyou Xu (Joe)
b115a22828 tests/assembly: add minicore compiletest self-test
Check that `minicore` cannot be used with `run-{pass,fail}` tests.
2024-10-31 18:20:11 +08:00
Krasimir Georgiev
e4f793a1aa riscv-soft-abi-with-float-features.rs: adapt for LLVM 20 2024-10-28 13:43:03 +00:00
bors
b8bb2968ce Auto merge of #132079 - fmease:rollup-agrd358, r=fmease
Rollup of 9 pull requests

Successful merges:

 - #130991 (Vectorized SliceContains)
 - #131928 (rustdoc: Document `markdown` module.)
 - #131955 (Set `signext` or `zeroext` for integer arguments on RISC-V and LoongArch64)
 - #131979 (Minor tweaks to `compare_impl_item.rs`)
 - #132036 (Add a test case for #131164)
 - #132039 (Specialize `read_exact` and `read_buf_exact` for `VecDeque`)
 - #132060 ("innermost", "outermost", "leftmost", and "rightmost" don't need hyphens)
 - #132065 (Clarify documentation of `ptr::dangling()` function)
 - #132066 (Fix a typo in documentation of `pointer::sub_ptr()`)

r? `@ghost`
`@rustbot` modify labels: rollup
2024-10-23 22:28:57 +00:00
Graydon Hoare
e14d6d8314
Add wasm32v1-none target (compiler-team/#791) 2024-10-22 23:04:44 -07:00
Asuna
57bffe1d59 Set signext or zeroext for integer arguments on LoongArch64 2024-10-23 04:42:21 +02:00
Asuna
6b65524620 Set signext or zeroext for integer arguments on RISC-V 2024-10-23 04:42:03 +02:00
bors
8bf64f106a Auto merge of #131871 - RalfJung:x86-32-float, r=workingjubilee
x86-32 float return for 'Rust' ABI: treat all float types consistently

This helps with https://github.com/rust-lang/rust/issues/131819: for our own ABI on x86-32, we want to *never* use the float registers. The previous logic only considered F32 and F64, but skipped F16 and F128. So I made the logic just apply to all float types.

try-job: i686-gnu
try-job: i686-gnu-nopt
2024-10-22 22:36:59 +00:00
Ralf Jung
09068192f8 adjust asm test 2024-10-22 12:21:00 +01:00
Jubilee
1b24c6fc14
Rollup merge of #131807 - beetrees:riscv-target-abi, r=workingjubilee
Always specify `llvm_abiname` for RISC-V targets

For RISC-V targets, when `llvm_abiname` is not specified LLVM will infer the ABI from the target features, causing #116344 to occur. This PR adds the correct `llvm_abiname` to all RISC-V targets where it is missing (which are all soft-float targets), and adds a test to prevent future RISC-V targets from accidentally omitting `llvm_abiname`. The only affect of this PR is that `-Ctarget-feature=+f` (or similar) will no longer affect the ABI on the modified targets.

<!-- homu-ignore:start -->
r? `@RalfJung`
<!--- homu-ignore:end -->
2024-10-21 20:32:01 -07:00
bors
a2a1206811 Auto merge of #131211 - bjorn3:rust_abi_follow_c_rules, r=nikic,jieyouxu
Return values larger than 2 registers using a return area pointer

LLVM and Cranelift disagree about how to return values that don't fit in the registers designated for return values. LLVM will force the entire return value to be passed by return area pointer, while Cranelift will look at each IR level return value independently and decide to pass it in a register or not, which would result in the return value being passed partially in registers and partially through a return area pointer.

While Cranelift may need to be fixed as the LLVM behavior is generally more correct with respect to the surface language, forcing this behavior in rustc itself makes it easier for other backends to conform to the Rust ABI and for the C ABI rustc already handles this behavior anyway.

In addition LLVM's decision to pass the return value in registers or using a return area pointer depends on how exactly the return type is lowered to an LLVM IR type. For example `Option<u128>` can be lowered as `{ i128, i128 }` in which case the x86_64 backend would use a return area pointer, or it could be passed as `{ i32, i128 }` in which case the x86_64 backend would pass it in registers by taking advantage of an LLVM ABI extension that allows using 3 registers for the x86_64 sysv call conv rather than the officially specified 2 registers.

This adjustment is only necessary for the Rust ABI as for other ABI's the calling convention implementations in rustc_target already ensure any return value which doesn't fit in the available amount of return registers is passed in the right way for the current target.

Helps with https://github.com/rust-lang/rustc_codegen_cranelift/issues/1525
cc https://github.com/bytecodealliance/wasmtime/issues/9250
2024-10-19 14:21:46 +00:00
bjorn3
cc7044b080 Fix test expectations for 32bit x86 2024-10-19 13:09:21 +00:00
beetrees
3ea91c05db
Always specify llvm_abiname for RISC-V targets 2024-10-17 02:07:02 +01:00
Matthias Krüger
fc81a7c1d5
Rollup merge of #131208 - mustartt:aix-call-abi, r=davidtwco
ABI: Pass aggregates by value on AIX

On AIX we pass aggregates byval. Adds new ABI for AIX for powerpc64.

313ad85dfa/clang/lib/CodeGen/Targets/PPC.cpp (L216)

Fixes the following 2 testcases on AIX:
```
tests/ui/abi/extern/extern-pass-TwoU16s.rs
tests/ui/abi/extern/extern-pass-TwoU8s.rs
```
2024-10-11 15:36:51 +02:00
Zalathar
96224d80ce compiletest: Remove the magic hacks for finding output with lto=thin
This hack was intended to handle the case where `-Clto=thin` causes the
compiler to emit multiple output files (when producing LLVM-IR or assembly).

The hack only affects 4 tests, of which 3 are just meta-tests for the hack
itself. The one remaining test that motivated the hack currently doesn't even
need it!

(`tests/codegen/issues/issue-81408-dllimport-thinlto-windows.rs`)
2024-10-11 11:28:42 +11:00
Henry Jiang
e502a7f13a add aix aggregate test 2024-10-07 20:40:55 -04:00
Folkert de Vries
bc0a9543a3 more asm! -> naked_asm! in tests 2024-10-06 18:12:25 +02:00
Henri Lunnikivi
fe658e1fe4 Add assembly tests to satisfy 'tidy' 2024-10-05 12:14:35 +03:00
Jubilee
b88f56f862
Rollup merge of #130453 - randomPoison:trusty-x86, r=pnkfelix
Add x86_64-unknown-trusty as tier 3 target

This PR adds a third target for the Trusty platform, `x86_64-unknown-trusty`.

Please let me know if an MCP is required. https://github.com/rust-lang/compiler-team/issues/582 was made when adding the first two targets, I can make another one for the new target as well if needed.

# Target Tier Policy Acknowledgements

> A tier 3 target must have a designated developer or developers (the "target maintainers") on record to be CCed when issues arise regarding the target. (The mechanism to track and CC such developers may evolve over time.)

- Nicole LeGare (```@randomPoison)```
- Andrei Homescu (```@ahomescu)```
- Chris Wailes (chriswailes@google.com)
- As a fallback trusty-dev-team@google.com can be contacted

Note that this does not reflect the maintainers currently listed in [`trusty.md`](c52c23b6f4/src/doc/rustc/src/platform-support/trusty.md). #130452 is currently open to update the list of maintainers in the documentation.

> Targets must use naming consistent with any existing targets; for instance, a target for the same CPU or OS as an existing Rust target should use the same name for that CPU or OS. Targets should normally use the same names and naming conventions as used elsewhere in the broader ecosystem beyond Rust (such as in other toolchains), unless they have a very good reason to diverge. Changing the name of a target can be highly disruptive, especially once the target reaches a higher tier, so getting the name right is important even for a tier 3 target.

The new target `x86_64-unknown-trusty` follows the existing naming convention for similar targets.

> Target names should not introduce undue confusion or ambiguity unless absolutely necessary to maintain ecosystem compatibility. For example, if the name of the target makes people extremely likely to form incorrect beliefs about what it targets, the name should be changed or augmented to disambiguate it.

👍

> Tier 3 targets may have unusual requirements to build or use, but must not create legal issues or impose onerous legal terms for the Rust project or for Rust developers or users.

There are no known legal issues or license incompatibilities.

> Neither this policy nor any decisions made regarding targets shall create any binding agreement or estoppel by any party. If any member of an approving Rust team serves as one of the maintainers of a target, or has any legal or employment requirement (explicit or implicit) that might affect their decisions regarding a target, they must recuse themselves from any approval decisions regarding the target's tier status, though they may otherwise participate in discussions.

👍

> Tier 3 targets should attempt to implement as much of the standard libraries as possible and appropriate (core for most targets, alloc for targets that can support dynamic memory allocation, std for targets with an operating system or equivalent layer of system-provided functionality), but may leave some code unimplemented (either unavailable or stubbed out as appropriate), whether because the target makes it impossible to implement or challenging to implement. The authors of pull requests are not obligated to avoid calling any portions of the standard library on the basis of a tier 3 target not implementing those portions.

This PR only adds the target. `std` support is being worked on and will be added in a future PR.

> The target must provide documentation for the Rust community explaining how to build for the target, using cross-compilation if possible. If the target supports running binaries, or running tests (even if they do not pass), the documentation must explain how to run such binaries or tests for the target, using emulation if possible or dedicated hardware if necessary.

👍

> Tier 3 targets must not impose burden on the authors of pull requests, or other developers in the community, to maintain the target. In particular, do not post comments (automated or manual) on a PR that derail or suggest a block on the PR based on a tier 3 target. Do not send automated messages or notifications (via any medium, including via ```@)``` to a PR author or others involved with a PR regarding a tier 3 target, unless they have opted into such messages.

👍

> Patches adding or updating tier 3 targets must not break any existing tier 2 or tier 1 target, and must not knowingly break another tier 3 target without approval of either the compiler team or the maintainers of the other tier 3 target.

👍

> Tier 3 targets must be able to produce assembly using at least one of rustc's supported backends from any host target. (Having support in a fork of the backend is not sufficient, it must be upstream.)

👍
2024-10-04 14:11:34 -07:00
Matthias Krüger
508b433e27
Rollup merge of #130549 - biabbas:riscv32_wrs_vxworks, r=nnethercote
Add RISC-V vxworks targets

Risc-V 32 and RISC-V 64 targets are to be added in the target list.
2024-09-25 10:09:22 +02:00
Trevor Gross
1f52c07528
Rollup merge of #130752 - tdittr:cmse-assembly-tests, r=jieyouxu
Improve assembly test for CMSE ABIs

Tracking issues: #75835 #81391

This ensures the code-gen for these ABIs does not change silently. There is a small chance that this code-gen might change, however even GCC (https://godbolt.org/z/16arxab5x and https://godbolt.org/z/16arxab5x) generates almost the same assembly for these ABIs. I hope the notes in the comments should help fix the tests if it ever breaks.
2024-09-24 19:47:49 -04:00
Michael Goulet
4d0b44ab5b
Rollup merge of #130750 - heiher:loong-linux-ohos-tier3, r=jieyouxu
Add new Tier-3 target: `loongarch64-unknown-linux-ohos`

MCP: https://github.com/rust-lang/compiler-team/issues/784
2024-09-23 23:49:12 -04:00
Tamme Dittrich
3d168c28f6 Improve assembly test for CMSE ABIs
This ensures the code-gen for these ABIs does not change silently.

Co-authored-by: Folkert <folkert@folkertdev.nl>
2024-09-23 18:57:38 +02:00
Xiaotian Wu
9ab704612a Add new Tier-3 target: loongarch64-unknown-linux-ohos
MCP: https://github.com/rust-lang/compiler-team/issues/784

Co-authored-by: WANG Rui <wangrui@loongson.cn>
2024-09-23 23:06:14 +08:00
Jubilee
021ae2c7fd
Rollup merge of #130657 - arttet:fix/fuchsia, r=jieyouxu
Remove x86_64-fuchsia and aarch64-fuchsia target aliases

Closes #106649.
2024-09-23 07:54:45 -07:00
Folkert
a41c209ef3 Add assembly test for the cmse unstable features
verifies that the correct return instructions are emitted.

Co-authored-by: Tamme Dittrich <tamme@tweedegolf.com>
2024-09-21 13:05:23 +02:00
Artyom Tetyukhin
019435b265
Remove x86_64-fuchsia and aarch64-fuchsia target aliases 2024-09-21 13:29:00 +04:00
Artyom Tetyukhin
340b38ed67
Add arm64e-apple-tvos target 2024-09-20 18:53:09 +04:00
B I Mohammed Abbas
485e90f1a7 Add Vxworks RISC-V targets 2024-09-20 16:15:55 +05:30
Josh Stone
6fd8a50680 Update the minimum external LLVM to 18 2024-09-18 13:53:31 -07:00
Nicole LeGare
ae5d448a26 Add x86_64-unknown-trusty as tier 3 2024-09-16 15:47:54 -07:00
Raoul Strackx
11b42d2763 Ignore reduce-fadd-unordered on SGX platform 2024-09-16 16:54:48 +02:00
Jubilee
68758c0560
Rollup merge of #130325 - workingjubilee:plus-minus-zero-redux, r=RalfJung,jieyouxu
Use -0.0 in `intrinsics::simd::reduce_add_unordered`

-0.0 is the actual neutral additive float, not +0.0, and this matters to codegen.

try-job: aarch64-gnu
2024-09-15 23:51:25 -07:00
Jubilee Young
ab8c202527 Use -0.0 in intrinsics::simd::reduce_add_unordered
-0.0 is the actual neutral additive float, not +0.0, and this matters to codegen.
2024-09-15 16:40:23 -07:00
Tim Neumann
cf006f375d
small_data_threshold.rs: Adapt to LLVM head changes 2024-09-12 09:53:59 +02:00
bors
1f51450c68 Auto merge of #117465 - paulmenage:small-data-limit, r=compiler-errors
Add -Z small-data-threshold

This flag allows specifying the threshold size above which LLVM should not consider placing small objects in a `.sdata` or `.sbss` section.

Support is indicated in the target options via the
small-data-threshold-support target option, which can indicate either an
LLVM argument or an LLVM module flag.  To avoid duplicate specifications
in a large number of targets, the default value for support is
DefaultForArch, which is translated to a concrete value according to the
target's architecture.
2024-09-12 04:27:08 +00:00
Paul Menage
3810386bbe Add -Z small-data-threshold
This flag allows specifying the threshold size above which LLVM should
not consider placing small objects in a .sdata or .sbss section.

Support is indicated in the target options via the
small-data-threshold-support target option, which can indicate either an
LLVM argument or an LLVM module flag.  To avoid duplicate specifications
in a large number of targets, the default value for support is
DefaultForArch, which is translated to a concrete value according to the
target's architecture.
2024-09-10 12:19:16 -07:00
Scott McMurray
d2309c2a9d Ban non-array SIMD 2024-09-09 19:39:43 -07:00
Samuel Thibault
7626015848 added support for GNU/Hurd on x86_64 2024-09-08 23:37:07 +02:00
Michael Goulet
bc2244f027
Rollup merge of #129940 - liushuyu:s390x-target-features, r=RalfJung
s390x: Fix a regression related to backchain feature

In #127506, we introduced a new IBM Z-specific target feature, `backchain`.

This particular `target-feature` was available as a function-level attribute in LLVM 17 and below, so some hacks were used to avoid blowing up LLVM when querying the supported LLVM features.

This led to an unfortunate regression where `cfg!(target-feature = "backchain")` will always return true.

This pull request aims to fix this issue, and a test has been introduced to ensure it will never happen again.

Fixes #129927.

r? `@RalfJung`
2024-09-07 14:21:22 +03:00
Michael Goulet
adcee23a95
Rollup merge of #129468 - Rajveer100:hack-to-avoid-function-merging, r=Mark-Simulacrum
[testsuite][cleanup] Remove all usages of `dont_merge` hack to avoid function merging

Resolves #129438

The `-Zmerge-functions=disabled` compile flag exists for this purpose.
2024-09-07 14:21:19 +03:00
liushuyu
6e4c5c10b9 tests: add an assembly scanning test for s390x backchain switch 2024-09-04 08:10:53 -06:00
Jan Sommer
124454cda8 rtems: Add spec file for arm_rtems6_eabihf 2024-09-03 09:20:49 +02:00
Jakub Beránek
47e6b5deed Revert "Auto merge of #127537 - veluca93:struct_tf, r=BoxyUwU"
This reverts commit acb4e8b625, reversing
changes made to 100fde5246.
2024-09-01 16:35:53 +02:00
bors
1a1cc050d8 Auto merge of #127897 - nyurik:add-qnx-70-target, r=saethlin
add `aarch64_unknown_nto_qnx700` target - QNX 7.0 support for aarch64le

This backports the QNX 7.1 aarch64 implementation to 7.0.

* [x] required `-lregex` disabled, see https://github.com/rust-lang/libc/pull/3775 (released in libc 0.2.156)
* [x] uses `libgcc.a` instead of `libgcc_s.so` (7.0 used ancient GCC 5.4 which didn't have gcc_s)
* [x] a fix in `backtrace` crate to support stack traces https://github.com/rust-lang/backtrace-rs/pull/648

This PR bumps libc dependency to 0.2.158

CC: to the folks who did the [initial implementation](https://doc.rust-lang.org/rustc/platform-support/nto-qnx.html): `@flba-eb,` `@gh-tr,` `@jonathanpallant,` `@japaric`

# Compile target

```bash
# Configure qcc build environment
source _path_/_to_/qnx7.0/qnxsdp-env.sh

# Tell rust to use qcc when building QNX 7.0 targets
export build_env='
    CC_aarch64-unknown-nto-qnx700=qcc
    CFLAGS_aarch64-unknown-nto-qnx700=-Vgcc_ntoaarch64le_cxx
    CXX_aarch64-unknown-nto-qnx700=qcc
    AR_aarch64_unknown_nto_qnx700=ntoaarch64-ar'

# Build rust compiler, libs, and the remote test server
env $build_env ./x.py build \
  --target x86_64-unknown-linux-gnu,aarch64-unknown-nto-qnx700 \
  rustc library/core library/alloc library/std src/tools/remote-test-server

rustup toolchain link stage1 build/host/stage1
```

# Compile "hello world"

```bash
source _path_/_to_/qnx7.0/qnxsdp-env.sh

cargo new hello_world
cd hello_world
cargo +stage1 build --release --target aarch64-unknown-nto-qnx700
```

# Configure a remote for testing

Do this from a new shell - we will need to run more commands in the previous one.  I ran into these two issues, and found some workarounds.

* Temporary dir might not work properly
* Default `remote-test-server` has issues binding to an address

```
# ./remote-test-server
starting test server
thread 'main' panicked at src/tools/remote-test-server/src/main.rs:175:29:
called `Result::unwrap()` on an `Err` value: Os { code: 249, kind: AddrNotAvailable, message: "Can't assign requested address" }
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
```

Specifying `--bind` param actually fixes that, and so does setting `TMPDIR` properly.

```bash
# Copy remote-test-server to remote device. You may need to use sftp instead.
# ATTENTION: Note that the path is different from the one in the remote testing documentation for some reason
scp ./build/x86_64-unknown-linux-gnu/stage1-tools-bin/remote-test-server  qnxdevice:/path/

# Run ssh with port forwarding - so that rust tester can connect to the local port instead
ssh -L 12345:127.0.0.1:12345 qnxdevice

# on the device, run
rm -rf tmp && mkdir -p tmp && TMPDIR=$PWD/tmp ./remote-test-server --bind 0.0.0.0:12345
```

# Run test suit

Assume all previous environment variables are still set, or re-init them

```bash
export TEST_DEVICE_ADDR="localhost:12345"

# tidy needs to be skipped due to using un-published libc dependency
export exclude_tests='
    --exclude src/bootstrap
    --exclude src/tools/error_index_generator
    --exclude src/tools/linkchecker
    --exclude src/tools/tidy
    --exclude tests/ui-fulldeps
    --exclude rustc
    --exclude rustdoc
    --exclude tests/run-make-fulldeps'

env $build_env ./x.py test  $exclude_tests --stage 1 --target aarch64-unknown-nto-qnx700
```

try-job: dist-x86_64-msvc
2024-09-01 08:00:25 +00:00
Rajveer
b324fcb169 [testsuite][cleanup] Remove all usages of dont_merge hack to avoid function merging
Resolves #129438

The `-Zmerge-functions=disabled` compile flag exists for this purpose.
2024-08-31 01:12:41 +05:30
Yuri Astrakhan
f41e0bb41d Squashed aarch64_unknown_nto_qnx700 support 2024-08-30 01:19:55 -04:00
Luca Versari
7eb4cfeace Implement RFC 3525. 2024-08-28 09:54:23 +02:00