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Auto merge of #130987 - thejpster:revise-arm-platform-notes-soft-float, r=ehuss
Revise arm platform notes regarding soft float This PR updates the Arm microcontroller platform docs to recommend `-fpregs` instead of `+soft-float` as [discussed on Zulip](https://rust-lang.zulipchat.com/#narrow/stream/131828-t-compiler/topic/.60-Ctarget-feature.3D.2Bsoft-float.60.20considered.20harmful)
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@ -42,15 +42,14 @@ their own document.
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There are two 32-bit instruction set architectures (ISAs) defined by Arm:
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- The [*A32 ISA*][a32-isa], with fixed-width 32-bit instructions. Previously
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known as the *Arm* ISA, this originated with the original Arm1 of 1985 and has
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known as the *Arm* ISA, this originated with the original ARM1 of 1985 and has
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been updated by various revisions to the architecture specifications ever
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since.
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- The [*T32 ISA*][t32-isa], with a mix of 16-bit and 32-bit width instructions.
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Note that this term includes both the original 16-bit width *Thumb* ISA
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introduced with the Armv4T architecture in 1994, and the later 16/32-bit sized
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*Thumb-2* ISA introduced with the Armv6T2 architecture in 2003.
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Again, these ISAs have been revised by subsequent revisions to the relevant Arm
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*Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. Again, these
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ISAs have been revised by subsequent revisions to the relevant Arm
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architecture specifications.
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There is also a 64-bit ISA with fixed-width 32-bit instructions called the *A64
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@ -106,10 +105,14 @@ features you do not have available, leaving you with the optimized instruction
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scheduling and support for the features you do have. More details are available
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in the detailed target-specific documentation.
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**Note:** Many target-features are currently unstable and subject to change, and
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<div class="warning">
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Many target-features are currently unstable and subject to change, and
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if you use them you should disassemble the compiler output and manually inspect
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it to ensure only appropriate instructions for your CPU have been generated.
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</div>
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If you wish to use the *target-cpu* and *target-feature* options, you can add
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them to your `.cargo/config.toml` file alongside any other flags your project
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uses (likely linker related ones):
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@ -35,9 +35,9 @@ to use these flags.
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| CPU | FPU | DSP | Target CPU | Target Features |
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| ---------- | --- | --- | ----------- | --------------- |
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| Any | No | Yes | None | None |
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| Cortex-M4 | No | Yes | `cortex-m4` | `+soft-float` |
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| Cortex-M4 | No | Yes | `cortex-m4` | `-fpregs` |
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| Cortex-M4F | SP | Yes | `cortex-m4` | None |
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| Cortex-M7 | No | Yes | `cortex-m7` | `+soft-float` |
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| Cortex-M7 | No | Yes | `cortex-m7` | `-fpregs` |
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| Cortex-M7F | SP | Yes | `cortex-m7` | `-fp64` |
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| Cortex-M7F | DP | Yes | `cortex-m7` | None |
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@ -50,6 +50,13 @@ to use these flags.
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| Cortex-M7F | SP | Yes | `cortex-m7` | `-fp64` |
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| Cortex-M7F | DP | Yes | `cortex-m7` | None |
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<div class="warning">
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Never use the `-fpregs` *target-feature* with the `thumbv7em-none-eabihf` target
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as it will cause compilation units to have different ABIs, which is unsound.
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</div>
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### Arm Cortex-M4 and Arm Cortex-M4F
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The target CPU is `cortex-m4`.
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@ -59,7 +66,7 @@ The target CPU is `cortex-m4`.
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* enabled by default with this *target*
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* Cortex-M4F has a single precision FPU
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* support is enabled by default with this *target-cpu*
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* disable support using the `+soft-float` feature (`eabi` only)
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* disable support using the `-fpregs` *target-feature* (`eabi` only)
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### Arm Cortex-M7 and Arm Cortex-M7F
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@ -71,4 +78,4 @@ The target CPU is `cortex-m7`.
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* Cortex-M7F have either a single-precision or double-precision FPU
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* double-precision support is enabled by default with this *target-cpu*
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* opt-out by using the `-f64` *target-feature*
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* disable support entirely using the `+soft-float` feature (`eabi` only)
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* disable support entirely using the `-fpregs` *target-feature* (`eabi` only)
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@ -39,22 +39,22 @@ to use these flags.
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| CPU | FPU | DSP | MVE | Target CPU | Target Features |
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| ----------- | --- | --- | --------- | ------------- | --------------------- |
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| Unspecified | No | No | No | None | None |
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| Cortex-M33 | No | No | No | `cortex-m33` | `+soft-float,-dsp` |
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| Cortex-M33 | No | Yes | No | `cortex-m33` | `+soft-float` |
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| Cortex-M33 | No | No | No | `cortex-m33` | `-fpregs,-dsp` |
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| Cortex-M33 | No | Yes | No | `cortex-m33` | `-fpregs` |
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| Cortex-M33 | SP | No | No | `cortex-m33` | `-dsp` |
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| Cortex-M33 | SP | Yes | No | `cortex-m33` | None |
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| Cortex-M35P | No | No | No | `cortex-m35p` | `+soft-float,-dsp` |
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| Cortex-M35P | No | Yes | No | `cortex-m35p` | `+soft-float` |
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| Cortex-M35P | No | No | No | `cortex-m35p` | `-fpregs,-dsp` |
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| Cortex-M35P | No | Yes | No | `cortex-m35p` | `-fpregs` |
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| Cortex-M35P | SP | No | No | `cortex-m35p` | `-dsp` |
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| Cortex-M35P | SP | Yes | No | `cortex-m35p` | None |
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| Cortex-M55 | No | Yes | No | `cortex-m55` | `+soft-float,-mve` |
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| Cortex-M55 | No | Yes | No | `cortex-m55` | `-fpregs,-mve` |
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| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` |
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| Cortex-M55 | No | Yes | Int | `cortex-m55` | `+soft-float,-mve.fp` |
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| Cortex-M55 | No | Yes | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`|
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| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` |
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| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None |
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| Cortex-M85 | No | Yes | No | `cortex-m85` | `+soft-float,-mve` |
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| Cortex-M85 | No | Yes | No | `cortex-m85` | `-fpregs,-mve` |
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| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` |
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| Cortex-M85 | No | Yes | Int | `cortex-m85` | `+soft-float,-mve.fp` |
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| Cortex-M85 | No | Yes | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`|
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| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` |
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| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None |
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@ -74,6 +74,19 @@ to use these flags.
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| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` |
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| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None |
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*Technically* you can use this hard-float ABI on a CPU which has no FPU but does
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have Integer MVE, because MVE provides the same set of registers as the FPU
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(including `s0` and `d0`). The particular set of flags that might enable this
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unusual scenario are currently not recorded here.
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<div class="warning">
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Never use the `-fpregs` *target-feature* with the `thumbv8m.main-none-eabihf`
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target as it will cause compilation units to have different ABIs, which is
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unsound.
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</div>
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### Arm Cortex-M33
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The target CPU is `cortex-m33`.
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@ -83,7 +96,7 @@ The target CPU is `cortex-m33`.
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* enabled by default with this *target-cpu*
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* Has an optional single precision FPU
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* support is enabled by default with this *target-cpu*
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* disable support using the `+soft-float` feature (`eabi` only)
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* disable support using the `-fpregs` *target-feature* (`eabi` only)
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### Arm Cortex-M35P
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@ -94,7 +107,7 @@ The target CPU is `cortex-m35p`.
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* enabled by default with this *target-cpu*
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* Has an optional single precision FPU
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* support is enabled by default with this *target-cpu*
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* disable support using the `+soft-float` feature (`eabi` only)
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* disable support using the `-fpregs` *target-feature* (`eabi` only)
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### Arm Cortex-M55
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@ -106,7 +119,7 @@ The target CPU is `cortex-m55`.
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* Has an optional double-precision FPU that also supports half-precision FP16
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values
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* support is enabled by default with this *target-cpu*
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* disable support using the `+soft-float` feature (`eabi` only)
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* disable support using the `-fpregs` *target-feature* (`eabi` only)
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* Has optional support for M-Profile Vector Extensions
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* Also known as *Helium Technology*
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* Available with only integer support, or both integer/float support
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@ -125,7 +138,7 @@ The target CPU is `cortex-m85`.
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* Has an optional double-precision FPU that also supports half-precision FP16
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values
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* support is enabled by default with this *target-cpu*
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* disable support using the `+soft-float` feature (`eabi` only)
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* disable support using the `-fpregs` *target-feature* (`eabi` only)
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* Has optional support for M-Profile Vector Extensions
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* Also known as *Helium Technology*
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* Available with only integer support, or both integer/float support
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