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Refine instruction_set inline rules
Previously an exact match of the `instruction_set` attribute was required for an MIR inline to be considered. This change checks for an exact match *only* if the callee sets an `instruction_set` in the first place. When the callee does not declare an instruction set then it is considered to be platform agnostic code and it's allowed to be inline'd into the caller.
This commit is contained in:
Lokathor
parent
68f77297c0
commit
ea47943212
@ -375,7 +375,12 @@ impl<'tcx> Inliner<'tcx> {
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return Err("incompatible sanitizer set");
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}
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if callee_attrs.instruction_set != self.codegen_fn_attrs.instruction_set {
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// Two functions are compatible if the callee has no attribute (meaning
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// that it's codegen agnostic), or sets an attribute that is identical
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// to this function's attribute.
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if callee_attrs.instruction_set.is_some()
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&& callee_attrs.instruction_set != self.codegen_fn_attrs.instruction_set
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{
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return Err("incompatible instruction set");
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}
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@ -453,6 +458,15 @@ impl<'tcx> Inliner<'tcx> {
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if ty.needs_drop(tcx, self.param_env) && let Some(unwind) = unwind {
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work_list.push(unwind);
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}
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} else if callee_attrs.instruction_set != self.codegen_fn_attrs.instruction_set
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&& matches!(term.kind, TerminatorKind::InlineAsm { .. })
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{
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// During the attribute checking stage we allow a callee with no
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// instruction_set assigned to count as compatible with a function that does
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// assign one. However, during this stage we require an exact match when any
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// inline-asm is detected. LLVM will still possibly do an inline later on
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// if the no-attribute function ends up with the same instruction set anyway.
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return Err("Cannot move inline-asm across instruction sets");
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} else {
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work_list.extend(term.successors())
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}
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@ -6,14 +6,19 @@
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let _1: (); // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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let _2: (); // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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let _3: (); // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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+ scope 1 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:53:5: 53:30
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let _4: (); // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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+ scope 1 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:59:5: 59:30
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+ }
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+ scope 2 (inlined inline_always_and_using_inline_asm) { // at $DIR/inline_instruction_set.rs:60:5: 60:41
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+ scope 3 {
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+ }
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+ }
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bb0: {
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StorageLive(_1); // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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_1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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// mir::Constant
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// + span: $DIR/inline_instruction_set.rs:51:5: 51:24
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// + span: $DIR/inline_instruction_set.rs:57:5: 57:24
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// + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
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}
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@ -22,7 +27,7 @@
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StorageLive(_2); // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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_2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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// mir::Constant
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// + span: $DIR/inline_instruction_set.rs:52:5: 52:24
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// + span: $DIR/inline_instruction_set.rs:58:5: 58:24
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// + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
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}
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@ -31,14 +36,25 @@
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StorageLive(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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- // mir::Constant
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- // + span: $DIR/inline_instruction_set.rs:53:5: 53:28
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- // + span: $DIR/inline_instruction_set.rs:59:5: 59:28
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- // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
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- }
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-
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- bb3: {
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StorageDead(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
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_0 = const (); // scope 0 at $DIR/inline_instruction_set.rs:+0:18: +4:2
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return; // scope 0 at $DIR/inline_instruction_set.rs:+4:2: +4:2
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StorageLive(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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- _4 = inline_always_and_using_inline_asm() -> bb4; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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- // mir::Constant
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- // + span: $DIR/inline_instruction_set.rs:60:5: 60:39
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- // + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
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+ asm!("/* do nothing */", options((empty))) -> bb3; // scope 3 at $DIR/inline_instruction_set.rs:43:14: 43:38
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}
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- bb4: {
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+ bb3: {
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StorageDead(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
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_0 = const (); // scope 0 at $DIR/inline_instruction_set.rs:+0:18: +5:2
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return; // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
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}
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}
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@ -1,5 +1,7 @@
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// Checks that only functions with the compatible instruction_set attributes are inlined.
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//
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// A function is "compatible" when the *callee* has the same attribute or no attribute.
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//
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// compile-flags: --target thumbv4t-none-eabi
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// needs-llvm-components: arm
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@ -36,14 +38,18 @@ fn instruction_set_t32() {}
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#[inline]
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fn instruction_set_default() {}
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#[inline(always)]
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fn inline_always_and_using_inline_asm() {
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unsafe { asm!("/* do nothing */") };
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}
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// EMIT_MIR inline_instruction_set.t32.Inline.diff
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#[instruction_set(arm::t32)]
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pub fn t32() {
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instruction_set_a32();
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instruction_set_t32();
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// The default instruction set is currently
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// conservatively assumed to be incompatible.
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instruction_set_default();
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inline_always_and_using_inline_asm();
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}
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// EMIT_MIR inline_instruction_set.default.Inline.diff
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@ -51,4 +57,5 @@ pub fn default() {
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instruction_set_a32();
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instruction_set_t32();
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instruction_set_default();
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inline_always_and_using_inline_asm();
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}
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@ -5,15 +5,18 @@
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let mut _0: (); // return place in scope 0 at $DIR/inline_instruction_set.rs:+0:14: +0:14
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let _1: (); // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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let _2: (); // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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let _3: (); // in scope 0 at $DIR/inline_instruction_set.rs:+5:5: +5:30
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+ scope 1 (inlined instruction_set_t32) { // at $DIR/inline_instruction_set.rs:43:5: 43:26
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let _3: (); // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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let _4: (); // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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+ scope 1 (inlined instruction_set_t32) { // at $DIR/inline_instruction_set.rs:50:5: 50:26
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+ }
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+ scope 2 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:51:5: 51:30
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+ }
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bb0: {
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StorageLive(_1); // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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_1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
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// mir::Constant
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// + span: $DIR/inline_instruction_set.rs:42:5: 42:24
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// + span: $DIR/inline_instruction_set.rs:49:5: 49:24
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// + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
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}
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@ -22,25 +25,34 @@
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StorageLive(_2); // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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- _2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
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- // mir::Constant
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- // + span: $DIR/inline_instruction_set.rs:43:5: 43:24
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- // + span: $DIR/inline_instruction_set.rs:50:5: 50:24
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- // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
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- }
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-
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- bb2: {
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StorageDead(_2); // scope 0 at $DIR/inline_instruction_set.rs:+2:26: +2:27
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StorageLive(_3); // scope 0 at $DIR/inline_instruction_set.rs:+5:5: +5:30
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- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline_instruction_set.rs:+5:5: +5:30
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+ _3 = instruction_set_default() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+5:5: +5:30
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StorageLive(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
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- // mir::Constant
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- // + span: $DIR/inline_instruction_set.rs:51:5: 51:28
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- // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
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- }
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-
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- bb3: {
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StorageDead(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
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StorageLive(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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- _4 = inline_always_and_using_inline_asm() -> bb4; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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+ _4 = inline_always_and_using_inline_asm() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
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// mir::Constant
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// + span: $DIR/inline_instruction_set.rs:46:5: 46:28
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// + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
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// + span: $DIR/inline_instruction_set.rs:52:5: 52:39
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// + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
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}
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- bb3: {
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- bb4: {
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+ bb2: {
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StorageDead(_3); // scope 0 at $DIR/inline_instruction_set.rs:+5:30: +5:31
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_0 = const (); // scope 0 at $DIR/inline_instruction_set.rs:+0:14: +6:2
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return; // scope 0 at $DIR/inline_instruction_set.rs:+6:2: +6:2
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StorageDead(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
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_0 = const (); // scope 0 at $DIR/inline_instruction_set.rs:+0:14: +5:2
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return; // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
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}
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}
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